Drive control method applicable to timing controller, and drive circuit
A drive control method applicable to a timing controller and a drive circuit are provided. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.
1 . A drive control method, applicable to a timing controller, the method comprising:
controlling M signal output terminals of the timing controller to be connected to ground in a first phase, such that M source driver chips enter a low power consumption mode in the case that M source driver chips detect that signal input terminals are connected to ground, wherein the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode;
wherein the timing controller comprises a controller, a timing transmission circuit, and a pull-down circuit, wherein the pull-down circuit comprises a pull-down switch and a second pull-down resistor that are connected in series, the second pull-down resistor being a fixed-value resistor; and
controlling the M signal output terminals of the timing controller to be connected to ground in the first phase comprises:
by the controller controlling the timing transmission circuit to interrupt signal output in the first phase, and closing the pull-down switch in the first phase, such that the M signal output terminals are connected to ground in the first phase.
2 . The method according to claim 1 , wherein controlling the timing transmission circuit to interrupt the signal output in the first phase, and closing the pull-down switch in the first phase comprise:
by the controller interrupting the signal output by the timing transmission circuit by transmitting a first timing control signal to the timing transmission circuit in the first phase, and closing the pull-down switch by transmitting a second pull-down control signal to the pull-down circuit in the first phase.
3 . The method according to claim 1 , further comprising:
controlling the M signal output terminals not to be connected to ground in a second phase, such that the M source driver chips enter a low power consumption wakeup mode in the case that the M source driver chips detect that the signal input terminals are not connected to ground, wherein the second phase indicates a phase in which the M source driver chips are expected to enter the low power consumption wakeup mode.
4 . The method according to claim 3 , wherein a total duration of the first phase and the second phase is fixed, and a duration of the second phase is less than a reference duration.
5 . The method according to claim 4 , wherein the first phase and the second phase are two sub-phases in a horizontal-blanking phase, and the reference duration includes 48 clock periods.
6 . The method according to claim 4 , wherein the first phase and the second phase are two sub-phases in a vertical-blanking phase, and the reference duration includes 4000 clock periods.
7 . The method according to claim 4 , wherein the first phase and the second phase are two sub-phases in a horizontal-blanking phase, and the reference duration includes 48 clock periods; the timing controller is configured to store a first amount, the first amount is an amount of clock calibration data to be transmitted in the horizontal-blanking phase, wherein the first amount is acquired based on a duration of the horizontal-blanking phase, and the first amount is less than 48;
the method further comprises:
determining, upon entering the low power consumption mode in the horizontal-blanking phase, a total duration for transmitting the first amount of clock calibration data based on a duration for transmitting each clock calibration data; and
determining a time point of entering the low power consumption wakeup mode in the horizontal-blanking phase based on the total duration, and entering the low power consumption wakeup mode at the time point, so that clock calibration is performed within 48 clock periods ensured by one of configuration of physical layer parameters of the M source driver chips and structure optimization of a clock data recovery circuit.
8 . The method according to claim 4 , wherein the first phase and the second phase are two sub-phases in a vertical-blanking phase, and the reference duration includes 4000 clock periods; the timing controller is configured to store a second amount, the second amount is an amount of clock calibration data to be transmitted in the vertical-blanking phase, the second amount is acquired based on a duration of the vertical-blanking phase, the second amount is less than 4000;
the method further comprises:
determining, upon entering the low power consumption mode in the vertical-blanking phase, a total duration for transmitting the second amount of clock calibration data based on a duration for transmitting each clock calibration data; and
determining a time point of entering the low power consumption wakeup mode in the vertical-blanking phase based on the total duration, and entering the low power consumption wakeup mode at the time point.
9 . A non-transitory computer-readable storage medium, storing one or more computer programs, wherein the one or more computer programs, when loaded and run by a processor, cause the processor to perform the method as defined in claim 1 .
10 . A drive control method, applicable to a timing controller, the method comprising:
controlling M signal output terminals of the timing controller to be connected to ground in a first phase, such that M source driver chips enter a low power consumption mode in the case that M source driver chips detect that signal input terminals are connected to ground, wherein the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode; and
controlling the M signal output terminals not to be connected to ground in a second phase, such that the M source driver chips enter a low power consumption wakeup mode in the case that the M source driver chips detect that the signal input terminals are not connected to ground, wherein the second phase indicates a phase in which the M source driver chips are expected to enter the low power consumption wakeup mode;
wherein a total duration of the first phase and the second phase is fixed, and a duration of the second phase is less than a reference duration.
11 . The method according to claim 10 , wherein the timing controller comprises a controller, a timing transmission circuit, and a pull-down circuit comprising a first pull-down resistor;
wherein controlling the M signal output terminals of the timing controller to be connected to ground in the first phase comprises:
by the controller controlling the timing transmission circuit to interrupt signal output in the first phase, and reducing a resistance of the first pull-down resistor in the first phase, such that the M signal output terminals are connected to ground in the first phase; and
by the controller interrupting the signal output by the timing transmission circuit by transmitting a first timing control signal to the timing transmission circuit in the first phase, and reducing the resistance of the first pull-down resistor by transmitting a first pull-down control signal to the pull-down circuit in the first phase.
12 . The method according to claim 10 , wherein the timing controller comprises a controller, a timing transmission circuit, and a pull-down circuit, wherein the pull-down circuit comprises a pull-down switch and a second pull-down resistor that are connected in series, the second pull-down resistor being a fixed-value resistor; and
controlling the M signal output terminals of the timing controller to be connected to ground in the first phase comprises:
by the controller interrupting the signal output by the timing transmission circuit by transmitting a first timing control signal to the timing transmission circuit in the first phase, and closing the pull-down switch by transmitting a second pull-down control signal to the pull-down circuit in the first phase.
13 . The method according to claim 10 , wherein the first phase and the second phase are two sub-phases in a horizontal-blanking phase, and the reference duration includes 48 clock periods.
14 . The method according to claim 10 , wherein the first phase and the second phase are two sub-phases in a vertical-blanking phase, and the reference duration includes 4000 clock periods.
15 . The method according to claim 10 , wherein the first phase and the second phase are two sub-phases in a horizontal-blanking phase, and the reference duration includes 48 clock periods; the timing controller is configured to store a first amount, the first amount is an amount of clock calibration data to be transmitted in the horizontal-blanking phase, wherein the first amount is acquired based on a duration of the horizontal-blanking phase, and the first amount is less than 48;
the method further comprises:
determining, upon entering the low power consumption mode in the horizontal-blanking phase, a total duration for transmitting the first amount of clock calibration data based on a duration for transmitting each clock calibration data; and
determining a time point of entering the low power consumption wakeup mode in the horizontal-blanking phase based on the total duration, and entering the low power consumption wakeup mode at the time point, so that clock calibration is performed within 48 clock periods ensured by one of configuration of physical layer parameters of the M source driver chips and structure optimization of a clock data recovery circuit.
16 . The method according to claim 10 , wherein the first phase and the second phase are two sub-phases in a vertical-blanking phase, and the reference duration includes 4000 clock periods; the timing controller is configured to store a second amount, the second amount is an amount of clock calibration data to be transmitted in the vertical-blanking phase, the second amount is acquired based on a duration of the vertical-blanking phase, the second amount is less than 4000;
the method further comprises:
determining, upon entering the low power consumption mode in the vertical-blanking phase, a total duration for transmitting the second amount of clock calibration data based on a duration for transmitting each clock calibration data; and
determining a time point of entering the low power consumption wakeup mode in the vertical-blanking phase based on the total duration, and entering the low power consumption wakeup mode at the time point.
17 . A non-transitory computer-readable storage medium, storing one or more computer programs, wherein the one or more computer programs, when loaded and run by a processor, cause the processor to perform the method as defined in claim 10 .
18 . A drive circuit, comprising a timing controller and M source driver chips, wherein the timing controller comprises:
M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to the M source driver chips, M being a positive integer; and
a controller, a timing transmission circuit, and a pull-down circuit, wherein a first output terminal of the controller is connected to an input terminal of the timing transmission circuit, an output terminal of the timing transmission circuit is connected to the M signal output terminals, a second output terminal of the controller is connected to a control terminal of the pull-down circuit, a first connection terminal of the pull-down circuit is connected to the M signal output terminals, and a second connection terminal of the pull-down circuit is connected to ground;
wherein the controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, wherein the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.
19 . The drive circuit according to claim 18 , wherein the controller is further configured to control the pull-down circuit, such that the M signal output terminals are not connected to ground in a second phase, wherein the M source driver chips are in a low power consumption wakeup mode in the case that the M signal input terminals are not connected to ground, and the second phase indicates a phase in which the M source driver chips are expected to enter the low power consumption wakeup mode.
20 . The drive circuit according to claim 18 , wherein the pull-down circuit comprises a first pull-down resistor, and the controller is configured to: control the timing transmission circuit to interrupt signal output in the first phase, and reduce a resistance of the first pull-down resistor in the first phase, such that the M signal output terminals are connected to ground in the first phase.