Granted Patent B2

US 12,542,480 · App. 18/300,211 · Granted Feb 3, 2026

Inventors: Alexander Mayer (Treffen, AT); Jens Barrenscheen (Munich, DE); Christian Heiling (Graz, AT); Markus Zannoth (Neubiberg, DE)

Assignee: Infineon Technologies AG

H02M1/08H03K17/082H02M7/5387H03K2217/0063H03K2217/0072

Abstract

Claims (73)

1 . A power switch driver circuit, the circuit comprising:

an input terminal;

a detection circuit, configured to:

receive a switching signal from the input terminal; and

output and hold the received switching signal to a power switch for a first duration;

a configuration decoding circuit, configured to:

receive a communication signal from the input terminal;

decode the received communication signal; and

output configuration information decoded from the communication signal,

wherein the configuration information sets behavior for the power switch driver circuit; and

a window generation circuit configured to:

during a window comprising a second duration, maintain the switching signal from the detection circuit, wherein to maintain the switching signal comprises disabling the received switching signal; and

allow decoding of the received communication signal during the window, wherein the second duration starts and ends within the first duration.

2 . The power switch driver circuit of claim 1 , wherein the switching signal is a pulse-width modulated (PWM) signal comprising a duty cycle.

3 . The power switch driver circuit of claim 1 , wherein the configuration information comprises one or more of: slew rate, over-temperature limit, over-current limit, gate current, gate current shape, gate voltage, and dead-time.

4 . The power switch driver circuit of claim 1 , wherein the start and end of the second duration is based at least in part on a delay-time correlated to the switching signal.

5 . The power switch driver circuit of claim 4 ,

wherein the power switch driver circuit comprises a high-side driver circuit and a low-side driver circuit,

wherein the switching signal comprises a dead-time, and

wherein the delay-time is based at least in part on the dead-time.

6 . The power switch driver circuit of claim 1 ,

wherein the input terminal is a first input terminal, the power switch driver circuit further comprising a second input terminal;

wherein switching signals comprise a high-side switching signal and a low-side switching signal; and

wherein an input signal received at the second input terminal controls the second duration for the window.

7 . A method comprising:

receiving, by power switch driver circuitry, a switching signal at an input terminal to the power switch driver circuitry at a first time;

in response to receiving the switching signal:

supplying, by the power switch driver circuitry, a first drive signal to a control terminal of a power switch for a first duration; and

waiting, by the power switch driver circuitry, for a second duration, wherein the second duration is based on circuit characteristics of the power switch and characteristics of the power switch driver circuitry;

after the second duration, receiving, by the power switch driver circuitry and during the first duration, a second signal at the input terminal different from the switching signal;

analyzing, by the power switch driver circuitry, the received second signal;

determining, by the power switch driver circuitry, that the received second signal is a communication signal based on characteristics of the second signal;

decoding, by the power switch driver circuitry, information in the communication signal, wherein the information comprises configuration information;

determining, by the power switch driver circuitry, that a communication window within the first duration has ended;

in response to determining that the communication window has ended, preparing, by the power switch driver circuitry, to receive the switching signal at the input terminal;

receiving, by the power switch circuitry, the switching signal at the input terminal at a second time subsequent to the first time, and

in response to receiving the switching signal, supplying, by the power switch driver circuitry, a second drive signal to a control terminal of a power switch for a third duration.

8 . The method of claim 7 , wherein determining that the communication window has ended comprises determining that a time period for the communication window has expired.

9 . The method of claim 7 , further comprising, receiving, at a second input terminal, a shoot-through protection (STP) signal, wherein determining that the communication window has ended comprises determining that the STP signal has toggled.

10 . The method of claim 7 , wherein characteristics of the communication signal comprise a modulation scheme, wherein the modulation scheme includes one or more of: amplitude modulation (AM), frequency modulation (FM), pulse width modulation (PWM), pulse code modulation (PCM), local interconnect network (LIN), universal asynchronous receiver/transmitter (UART), controller area network (CAN), peripheral sensor interface (PSI), and PSI5.

11 . The method of claim 9 , wherein the configuration information comprises one or more of: slew rate, over-temperature limit, over-current limit, gate current, gate current shape, gate voltage, and dead-time.

12 . The method of claim 11 , further comprising, controlling, by the power switch driver circuitry, implementation of the received configuration data to ensure safe switching.

13 . The method of claim 9 , wherein the switching signal comprises: a rising edge, and a falling edge.

14 . A system comprising:

a controller comprising processing circuitry;

power switch driver circuitry comprising:

an input terminal configured to connect to the controller;

a detection circuit, configured to:

receive a switching signal from the input terminal; and

output and hold the received switching signal to a power switch for a first duration;

a configuration decoding circuit, configured to:

receive a communication signal from the input terminal;

decode the received communication signal; and

output configuration information decoded from the communication signal, wherein the configuration information sets behavior for the power switch driver circuitry; and

a window generation circuit configured to:

during a second duration comprising a window, maintain the switching signal from the detection circuit, wherein to maintain the switching signal comprises disabling detection of a subsequent switching signal; and

allow decoding of the received communication signal during the window, wherein the second duration starts and ends within the first duration.

15 . The system of claim 14 , wherein the controller is configured to:

operatively connect to the input terminal;

output the switching signal to the input terminal of the power switch driver circuitry; and

output the communication signal to the input terminal.

16 . The system of claim 15 , wherein the controller is configured to:

control an amount of time for the first duration and an amount of time for the second duration; and

extend the second duration and the window for decoding the communication signal.

17 . The system of claim 14 , wherein the start and end of the second duration is based at least in part on a delay-time correlated to the switching signal.

18 . The system of claim 17 ,

wherein the power switch driver circuitry comprises a high-side driver circuit and a low-side driver circuit,

wherein the switching signal comprises a dead-time, and

wherein the delay-time is based at least in part on the dead-time.

19 . The system of claim 14 ,

wherein the input terminal is a first input terminal, the power switch driver circuitry further comprising a second input terminal;

wherein switching signals from the controller comprises a high-side switching signal and a low-side switching signal; and

wherein an input signal received at the second input terminal controls the second duration for the window.

Assignments (1)

Continuity (1)

References Cited (16)