Multi-rate multistage digital compensator for nonlinear systems
An adaptable, multistage, multi-rate digital predistortion system that can increase the accuracy of the distortion applied to a power amplifier input signal is disclosed. Further, the digital predistortion system can be implemented using a reduced circuit area by reducing a number of coefficients used by the models applied to generate the distortion compensation signal. Further, the system can implement an improved digital predistortion adaptation engine that improves an adjacent channel leakage ratio of the digital predistortion system. Moreover, the system can compensate for non-linear impairments due to analog/RF circuits and systems and improve at least the following metrics: Error vector magnitude (EVM), adjacent channel leakage ratio (ACLR), spectrum emission mask (SEM), and power consumption of the circuits and systems. An example of circuits and systems is radio frequency power amplifier (RF PA).
1 . A digital predistortion system configured to distort a power amplifier input signal prior to being input to a power amplifier, the digital predistortion system comprising:
a first compensator comprising a first plurality of processing circuit blocks, wherein each processing circuit block of the first plurality of processing circuit blocks is configured to implement a first transformation function to modify a linearity of a first input signal that is input to the first compensator, wherein each processing circuit block of the first plurality of processing circuit blocks is connected in parallel within the first compensator, and wherein at least one processing circuit block of the first plurality of processing circuit blocks implements a different transformation function than at least one other processing circuit block of the first plurality of processing circuit blocks;
a second compensator connected in series with the first compensator, the second compensator comprising a second plurality of processing circuit blocks, wherein each processing circuit block of the second plurality of processing circuit blocks is configured to implement a second transformation function to modify a linearity of a second input signal that is input to the second compensator, wherein each processing circuit block of the second plurality of processing circuit blocks is connected in parallel within the second compensator, wherein the second input signal is based at least in part on an output of the first compensator, and wherein at least one processing circuit block of the second plurality of processing circuit blocks implements a different transformation function than at least one other processing circuit block of the second plurality of processing circuit blocks;
a set of one or more additional compensators connected in series between the first compensator and the second compensator; and
a first adder circuit configured to sum an output of each processing circuit block of the second plurality of processing circuit blocks to obtain a digital predistortion signal, wherein the first adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier.
2 . The digital predistortion system of claim 1 , wherein at least one of the first plurality of processing circuit blocks or the second plurality of processing circuit blocks implements a neural network.
3 . The digital predistortion system of claim 1 , wherein the second compensator further comprises the first adder circuit.
4 . The digital predistortion system of claim 1 , wherein each processing circuit block of the first plurality of processing circuit blocks is configured to generate an output that is supplied as an input to a corresponding processing circuit block of the second plurality of processing circuit blocks.
5 . The digital predistortion system of claim 1 , wherein the first compensator further comprises a second adder circuit configured to sum an output of each processing circuit block of the first plurality of processing circuit blocks to obtain an intermediary signal, wherein the intermediary signal is supplied as an input to the second compensator.
6 . The digital predistortion system of claim 1 , wherein at least one of the first compensator or the second compensator comprises a memory that stores signal samples enabling at least the first transformation function or the second transformation function to operate over a larger range of samples than a memoryless compensator.
7 . The digital predistortion system of claim 1 , wherein a combination of at least the first compensator and the second compensator is configured to generate a distortion of the power amplifier input signal such that a total system response of a system that includes the power amplifier is linear.
8 . The digital predistortion system of claim 1 , wherein the first compensator further comprises a plurality of down sampling circuits corresponding to the first plurality of processing circuit blocks, wherein each of the plurality of down sampling circuits is configured to down sample the first input signal to obtain a down sampled input signal that is input to the corresponding processing circuit block of the first plurality of processing circuit blocks.
9 . The digital predistortion system of claim 1 , wherein the first compensator further comprises a plurality of up sampling circuits corresponding to the first plurality of processing circuit blocks, wherein each of the plurality of up sampling circuits is configured to up sample an output of the corresponding processing circuit block of the first plurality of processing circuit blocks.
10 . The digital predistortion system of claim 1 , wherein at least the first transformation function or the second transformation function comprises one or more of a set of mathematical series or models configured to modify the linearity of an applied signal.
11 . The digital predistortion system of claim 1 , wherein at least the first transformation function or the second transformation function comprises one or more weighted coefficients that are set based on a digital predistortion adaptation circuit configured to determine the one or more weighted coefficients using an adaptive algorithm applied to an output of the power amplifier.
12 . The digital predistortion system of claim 1 , wherein at least the first transformation function or the second transformation function comprises one or more weighted coefficients that are set based on a digital predistortion adaptation circuit configured to determine the one or more weighted coefficients using back propagation and a least square estimate algorithm applied to an output of the power amplifier.
13 . A transceiver radio comprising:
a digital predistortion system connected in series with a power amplifier, the digital predistortion system comprising:
a plurality of compensator circuits connected in series, wherein each compensator circuit of the plurality of compensator circuits comprises a plurality of nonlinearity processing circuits connected in parallel and configured to implement a transformation function to modify a linearity of an input signal received at a first compensator circuit of the plurality of compensator circuits, and wherein at least one nonlinearity processing circuit of the plurality of nonlinearity processing circuits implements a different transformation function than at least one other nonlinearity processing circuit of the plurality of nonlinearity processing circuits, wherein the transformation function comprises one or more weighted coefficients that are set based on a digital predistortion adaptation circuit configured to determine the one or more weighted coefficients using back propagation; and
an adder circuit configured to sum an output of each nonlinearity processing circuit of the plurality of nonlinearity processing circuits of a last compensator circuit of the plurality of compensator circuits to obtain a digital predistortion signal, wherein the adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier.
14 . The transceiver radio of claim 13 , further comprising a crest factor reduction circuit configured to receive a transmit signal and to reduce a peak-to-peak average power ratio of the transmit signal to obtain a reduced peak-to-peak transmit signal, wherein the reduced peak-to-peak transmit signal is provided as an input signal to the digital predistortion system.
15 . The transceiver radio of claim 13 , further comprising the digital predistortion adaptation circuit configured to receive an output of the power amplifier and to configure the one or more weighted coefficients of the transformation function of at least one compensator circuit of the plurality of compensator circuits based at least in part on the output of the power amplifier.
16 . The transceiver radio of claim 13 , wherein at least one compensator circuit of the plurality of compensator circuits further comprises a plurality of down sampling circuits corresponding to the plurality of nonlinearity processing circuits, and wherein each of the plurality of down sampling circuits is configured to down sample the input signal to obtain a down sampled input signal that is input to the corresponding nonlinearity processing circuit of the plurality of nonlinearity processing circuits.
17 . The transceiver radio of claim 13 , wherein at least one compensator circuit of the plurality of compensator circuits further comprises a plurality of up sampling circuits corresponding to the plurality of nonlinearity processing circuits, and wherein each of the plurality of up sampling circuits is configured to up sample an output of the corresponding nonlinearity processing circuit of the plurality of nonlinearity processing circuits.
18 . A wireless device comprising:
an antenna configured to emit a signal received from a power amplifier;
the power amplifier;
a transceiver comprising a digital predistortion system connected in series with the power amplifier, the digital predistortion system comprising:
a plurality of compensator circuits connected in series, wherein each compensator circuit of the plurality of compensator circuits comprises a plurality of nonlinearity processing circuits connected in parallel and configured to implement a transformation function to modify a linearity of an input signal received at a first compensator circuit of the plurality of compensator circuits, and wherein at least one nonlinearity processing circuit of the plurality of nonlinearity processing circuits implements a different transformation function than at least one other nonlinearity processing circuit of the plurality of nonlinearity processing circuits; and
an adder circuit configured to sum an output of each nonlinearity processing circuit of the plurality of nonlinearity processing circuits of a last compensator circuit of the plurality of compensator circuits to obtain a digital predistortion signal, wherein the adder circuit is further configured to provide the digital predistortion signal as an input to the power amplifier;
a digital predistortion adaptation circuit configured to receive an output of the power amplifier and to configure one or more coefficients of the transformation function of at least one compensator circuit of the plurality of compensator circuits based at least in part on the output of the power amplifier, wherein the digital predistortion adaptation circuit is configured to determine the one or more coefficients using back propagation; and
a coupler configured to provide the output of the power amplifier to the digital predistortion adaptation circuit.