Timing margin sensor
A timing margin sensor includes a delay circuit to generate a calibrated delay that corresponds to a known delay value of a logic circuit. Circuitry locks a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value. A programmable selector adjusts the first delay to generate the calibrated delay, the calibrated delay including a timing margin component. Circuitry detects a change in supply voltage provided to the logic circuit based on a detected change in the calibrated delay. Clock adjustment circuitry selectively changes the clock period based on the detected change in the calibrated delay.
1 . A method of operation in a digital system, comprising:
calibrating a delay circuit to generate a first delay that corresponds to a known delay value of a logic circuit, the calibrating including
locking the first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value, and
adjusting the first delay with a programmable selector to generate a calibrated delay, the calibrated delay including a timing margin component; and
detecting a change in supply voltage provided to the logic circuit by monitoring the delay circuit for a change in the calibrated delay; and
compensating for the detected change in the calibrated delay by adjusting the clock period.
2 . The method of claim 1 , wherein the monitoring of the delay circuit for a change in the calibrated delay includes:
detecting the change in the calibrated delay to a second delay that differs from the calibrated delay by at least a threshold delay value.
3 . The method of claim 2 , wherein:
the threshold delay value is a programmable value that corresponds to a threshold timing margin.
4 . The method of claim 1 , wherein:
the locking of the first delay produced by the delay circuit to the clock period is performed by a locked-loop circuit.
5 . The method of claim 1 , wherein the adjusting of the first delay with the programmable selector to generate the calibrated delay includes:
selecting a first delayed version of the clock signal;
comparing the first delayed version of the clock signal to a next clock edge of the clock signal; and
adjusting the first delay based on a phase difference between the first delayed version of the clock signal and the next clock edge of the clock signal.
6 . The method of claim 5 , wherein the adjusting of the clock period includes:
changing the clock period to a first adjusted value;
determining whether a desired timing margin criteria is satisfied; and
selectively adjusting the clock period to a second adjusted value based on whether the desired timing margin criteria is satisfied.
7 . The method of claim 6 , wherein:
the changing of the clock period to the first adjusted value is responsive to receipt of the next clock edge of the clock signal; and
the selectively adjusting the clock period to the second adjusted value is responsive to receipt of a subsequent clock edge that immediately follows the next clock edge of the clock signal.
8 . A timing margin sensor, comprising:
a delay circuit to generate a first delay that corresponds to a known delay value of a logic circuit;
locked-loop circuitry to lock a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value;
a programmable selector to adjust the first delay to generate a calibrated delay, the calibrated delay including a timing margin component;
monitoring circuitry to detect a change in supply voltage provided to the logic circuit the corresponds to a detected change in the calibrated delay; and
clock adjustment circuitry to selectively change the clock period based on the detected change in the calibrated delay.
9 . The timing margin sensor of claim 8 , wherein:
the delay circuit comprises a digitally-controlled delay line of multiple delay elements.
10 . The timing margin sensor of claim 8 , wherein:
the programmable selector provides a coarse adjustment component to the first delay as a first component of the calibrated delay.
11 . The timing margin sensor of claim 10 , further comprising:
interpolator circuitry to provide a fine adjustment component to the first delay that is combined with the coarse adjustment component.
12 . The timing margin sensor of claim 8 , wherein the programmable selector is to select a first delayed version of the clock signal, and wherein the timing margin sensor further includes:
control circuitry to compare the first delayed version of the clock signal to a next clock edge of the clock signal, the control circuitry to adjust the first delay based on a phase difference between the first delayed version of the clock signal and the next clock edge of the clock signal.
13 . The timing margin sensor of claim 12 , wherein:
the clock adjustment circuitry is to change the clock period to a first adjusted value;
the control circuitry is to determine whether a desired timing margin criteria is satisfied in response to the first adjusted value of the clock period; and
wherein the clock adjustment circuitry is to selectively adjust the clock period to a second adjusted value based on whether the desired timing margin criteria is satisfied.
14 . The timing margin sensor of claim 13 , wherein:
the clock adjustment circuitry changes the clock period to the first adjusted value in response to receipt of the next clock edge of the clock signal; and
the clock adjustment circuitry selectively adjusts the clock period to the second adjusted value in response to receipt of a subsequent clock edge that immediately follows the next clock edge of the clock signal.
15 . A digital system, comprising:
a programmable clock generator to produce a system clock signal from a reference clock signal;
system circuitry synchronized to the system clock signal; and
a timing margin sensor including
a delay circuit to generate a first delay that corresponds to a known delay value of a system circuitry;
locked-loop circuitry to lock the first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value;
a programmable selector to adjust the first delay to generate a calibrated delay, the calibrated delay including a timing margin component; and
monitoring circuitry to detect a change in supply voltage provided to the system circuit that corresponds to a detected change in the calibrated delay; and
clock adjustment circuitry to selectively change the clock period based on the detected change in the calibrated delay.
16 . The digital system of claim 15 , wherein:
the programmable selector provides a coarse adjustment component to the first delay as a first component of the calibrated delay.
17 . The digital system of claim 16 , further comprising:
interpolator circuitry to provide a fine adjustment component to the first delay that is combined with the coarse adjustment component.
18 . The digital system of claim 15 , wherein the programmable selector is to select a first delayed version of the clock signal, and wherein the timing margin sensor further includes:
control circuitry to compare the first delayed version of the clock signal to a next clock edge of the clock signal, the control circuitry to adjust the first delay based on a phase difference between the first delayed version of the clock signal and the next clock edge of the clock signal.