Fin isolation structure for FinFET and method of forming the same
A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature formed over a substrate that includes a first fin and a second fin separated from each other by the isolation feature. The semiconductor device structure also includes an insulating fin structure formed in the isolation feature between the first fin and the second fin. The insulating fin structure includes a first insulating fin base partially formed within the isolation feature and a first insulating capping layer formed over a top surface of the first insulating fin base.
1 . A semiconductor device, comprising:
an isolation feature formed over a substrate;
a first fin and a second fin formed over the substrate and separated from each other by the isolation feature; and
a first structure formed in the isolation feature between the first fin and the second fin, comprising:
a first insulating layer partially formed within the isolation feature; and
a first capping layer formed over a top surface of the first insulating layer.
2 . The semiconductor device as claimed in claim 1 , wherein the first structure further comprises:
a second capping layer formed over the top surface of the first dielectric layer.
3 . The semiconductor device as claimed in claim 2 , wherein a top surface of the first capping layer is substantially level with a top surface of the second capping layer.
4 . The semiconductor device as claimed in claim 1 , wherein the first structure further comprises:
a second insulating layer covering a bottom surface of the first insulating layer and extending along sidewalls of the first insulating layer to reach at least a level of a top surface of the first capping layer.
5 . The semiconductor device as claimed in claim 4 , wherein the second insulating layer is made of a nitrogen-containing material or carbon- and nitrogen-containing material.
6 . The semiconductor device as claimed in claim 1 , further comprising:
a third fin adjacent to the second fin and separated from the first fin by the second fin; and
a second structure partially formed within the isolation feature between the second fin and the third fin, wherein the second structure has a top surface that is substantially level with a top surface of the first capping layer.
7 . The semiconductor device as claimed in claim 6 , wherein the second structure has a width smaller than a width of the first insulating layer and is made of a material that is different than that the first insulating layer is made of.
8 . A semiconductor device, comprising:
a first fin structure and a second fin structure disposed over a substrate;
an isolation feature between the first fin structure and the second fin structure; and
a structure disposed between the first fin structure and the second fin structure and over the isolation feature, comprising:
a first insulating layer;
a second insulating layer covering a bottom surface and sidewall surfaces of the first insulating layer; and
a first capping layer disposed over the first insulating layer.
9 . The semiconductor device as claimed in claim 8 , wherein the structure is spaced apart from the first fin structure by a first distance.
10 . The semiconductor device as claimed in claim 8 , wherein the first fin structure and the second fin structure are longitudinally oriented along a first direction, and the structure is longitudinally oriented along a second direction that is substantially parallel to the first direction.
11 . The semiconductor device as claimed in claim 8 , wherein the first capping layer is made of a high k material.
12 . The semiconductor device as claimed in claim 8 , wherein the first insulating layer is made of a nitrogen-containing material or carbon- and nitrogen-containing material.
13 . The semiconductor device as claimed in claim 8 , wherein a bottom surface of the structure is higher than a bottom surface of the isolation feature.
14 . The semiconductor device as claimed in claim 8 , wherein a top surface of the first insulating layer is higher than a top surface of the isolation feature.
15 . A semiconductor device, comprising:
an isolation feature;
a first fin, a second fin, and a third fin protruding from a top surface of the isolation feature, wherein the second fin is spaced apart from the first fin along a first direction, and the third fin is spaced apart from the first fin by a second direction being different from the first direction; and
a fin isolation structure, comprising:
a dielectric structure having a first portion and a second portion partially extending into the isolation feature, wherein the first portion is between the first fin and the second fin, and the second portion is between the first fin and the third fin; and
a dielectric layer covering bottom surfaces and sidewall surfaces of the first portion and the second portion, wherein the dielectric layer covering the first portion is covered by the isolation feature, and the dielectric layer covering the second portion passes through the isolation feature.
16 . The semiconductor device as claimed in claim 15 , wherein the fin isolation structure further comprises:
a first capping layer over the second portion of the dielectric structure in a third direction being different from the first direction and the second direction.
17 . The semiconductor device as claimed in claim 16 , wherein the fin isolation structure further comprises:
a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials.
18 . The semiconductor device as claimed in claim 17 , wherein a top surface of the dielectric layer is substantially level with a top surface of the first capping layer and a top surface of the second capping layer.
19 . The semiconductor device as claimed in claim 15 , further comprising:
a first gate structure and a second gate structure longitudinally extending along the first direction and spaced apart from each other along the second direction,
wherein the first gate structure covers the first fin and the second fin, and the second gate structure covers the third fin.
20 . The semiconductor device as claimed in claim 15 , wherein the dielectric layer covering the first portion of the dielectric structure is separated from the first fin and the second fin, and the dielectric layer covering the second portion of the dielectric structure is in direct contact with the first fin and the third fin.