Clock phase noise measurement circuit and method
A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.
1 . A circuit for measuring jitter in a jittery clock signal, comprising:
a digital sinusoid generator circuit clocked by the jittery clock signal and configured to generate a pulse density modulation (PDM) signal corresponding to a sinusoid waveform;
a modulator circuit configured to convert the PDM signal to an oscillating frequency signal and generate digital values indicative of oscillating frequency signal phase;
a sampling circuit clocked by the jittery clock signal and configured to sample the digital values indicative of oscillating frequency signal phase;
a digital differentiator circuit configured to generate a digital difference signal indicative of a difference between consecutive samples of the digital values indicative of oscillating frequency signal phase; and
an analyzer circuit configured to process the digital difference signal to determine a measurement of jitter in the jittery clock signal.
2 . The circuit of claim 1 , wherein the digital differentiator circuit and analyzer circuit are clocked by the jittery clock signal.
3 . The circuit of claim 1 , wherein said digital sinusoid generator circuit comprises a read only memory (ROM) storing pulse density modulation characteristics of the sinusoid waveform.
4 . The circuit of claim 1 , wherein the modulator circuit comprises:
a flip-flop configured to sample the PDM signal in response to the jittery clock signal to output a voltage;
a transconductance stage configured to convert the voltage to a current; and
a ring oscillator configured to generate the oscillating frequency signal in response to the current.
5 . The circuit of claim 4 , wherein the sampling circuit comprises a set of flip-flops configured to store values of digital bits output by stages of the ring oscillator in response to the jittery clock signal.
6 . The circuit of claim 1 , wherein the modulator circuit comprises a sigma-delta modulator.
7 . The circuit of claim 1 , wherein the measurement of jitter in the jittery clock signal is made without comparison of the jittery clock signal to a reference clock signal.
8 . The circuit of claim 1 , wherein the analyzer circuit processes the digital difference signal to determine a signal to noise ratio (SNR) value which is correlated to jitter.
9 . The circuit of claim 8 , wherein a relatively lower SNR value is indicative of a relatively higher level of jitter present in the jittery clock signal.
10 . The circuit of claim 1 , wherein the analyzer circuit is a spectrum analyzer configured to generate a frequency spectrum for said PDM signal and determine a signal to noise ratio (SNR) value for said frequency spectrum that is indicative of jitter presence, wherein a relatively lower SNR value is indicative of a relatively higher level of jitter present in the jittery clock signal.
11 . A method for measuring jitter in a jittery clock signal, comprising:
generating a pulse density modulation (PDM) signal corresponding to a sinusoid waveform, said PDM signal having a period set by pulses of the jittery clock signal;
converting the PDM signal to an oscillating frequency signal;
generating digital values indicative of phase of the oscillating frequency signal;
sampling the digital values indicative of phase of the oscillating frequency signal in response to the jittery clock signal;
determining a digital difference between consecutive samples of the digital values indicative of phase of the oscillating frequency signal; and
processing said digital difference to determine a measurement of jitter in the jittery clock signal.
12 . The method of claim 11 , wherein converting comprises:
sampling the PDM signal in response to the jittery clock signal to output a voltage;
converting the voltage to a current; and
generating the oscillating frequency signal in response to the current.
13 . The method of claim 11 , wherein converting the PDM signal and generating digital values comprises performing a sigma-delta modulation.
14 . The method of claim 11 , wherein the measurement of jitter in the jittery clock signal is made without comparison of the jittery clock signal to a reference clock signal.
15 . The method of claim 11 , wherein processing said digital difference comprises generating a frequency spectrum for said PDM signal and determining a signal to noise ratio (SNR) value for said frequency spectrum that is indicative of jitter presence.
16 . The method of claim 11 , wherein processing said digital difference comprises determining a signal to noise ratio (SNR) value which is correlated to jitter.
17 . The method of claim 16 , wherein a relatively lower SNR value is indicative of a relatively higher level of jitter present in the jittery clock signal.
18 . A circuit for measuring jitter in a jittery clock signal, comprising:
a first sampling circuit configured to sample a pulse density modulation (PDM) signal corresponding to a sinusoid waveform in response to the jittery clock signal to output a voltage;
a transconductance stage configured to convert the voltage to a current;
a ring oscillator configured to generate an oscillating frequency signal in response to the current;
a second sampling circuit clocked by the jittery clock signal and configured to sample bits output from stages of the ring oscillator;
a digital differentiator circuit configured to generate a digital difference signal indicative of a difference between consecutive samples of the bits output from stages of the ring oscillator; and
an analyzer circuit configured to process the digital difference signal to determine a measurement of jitter in the jittery clock signal.
19 . The circuit of claim 18 , wherein the second sampling circuit comprises a set of flip-flops configured to store bits output from stages of the ring oscillator in response to the jittery clock signal.
20 . The circuit of claim 18 , wherein the analyzer circuit processes the digital difference signal to determine a signal to noise ratio (SNR) value which is correlated to jitter, wherein a relatively lower SNR value is indicative of a relatively higher level of jitter present in the jittery clock signal.
21 . The circuit of claim 18 , wherein the analyzer circuit is a spectrum analyzer configured to generate a frequency spectrum for said PDM signal and determine a signal to noise ratio (SNR) value for said frequency spectrum that is indicative of jitter presence, wherein a relatively lower SNR value is indicative of a relatively higher level of jitter present in the jittery clock signal.