IP Library › Granted Patent US 12,547,266
Granted Patent B2
US 12,547,266 · App. 19/021,977 · Granted Feb 10, 2026

Touch sensor, display device, display module, and electronic device

Inventors: Hiroyuki Miyake (Aichi, JP); Takahiro Fukutome (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G06F3/0412G02F1/134372G02F1/13452G02F1/136286G02F1/1368G06F3/04164G06F3/04166G06F3/0443G06F3/0445G06F3/0446G06F3/045G06F3/047G02F1/13338G02F2202/104G06F2203/04104H10D86/423H10D86/60
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Quick Facts
Patent No.
US 12,547,266
App. No.
19/021,977
Granted
Feb 10, 2026
Kind
B2
Abstract

Sensing time of a touch sensor is shortened to increase responsiveness of touch sensing. A display device includes a gate driver, a plurality of touch sensors, and a plurality of touch wirings. The gate driver has a function of supplying a scan signal to the plurality of touch wirings at the same timing, and the touch sensors in different positions sense a plurality of touches at the same timing. In this manner, the responsiveness of touch sensing is increased. The gate driver has a function of controlling a scan signal for refreshing display and a scan signal used by the touch sensor for sensing.

Claims (48)

1 . A semiconductor device comprising a gate driver,

wherein the gate driver includes a decoder, a selection circuit, a first buffer, a second buffer, and a third buffer,

wherein the selection circuit is electrically connected to a first input signal line,

wherein the selection circuit comprises a shift register, a first switch, a second switch, and a third switch,

wherein a second terminal of the first switch is electrically connected to a first scan line through the first buffer,

wherein a second terminal of the second switch is electrically connected to a second scan line through the second buffer,

wherein a second terminal of the third switch is electrically connected to a touch wiring through the third buffer,

wherein the decoder is electrically connected to the first input signal line, a second input signal line, and an output signal line,

wherein the output signal line is electrically connected to an input terminal of the shift register and to a first terminal of the third switch,

wherein a first output terminal of the shift register is electrically connected to a first terminal of the first switch,

wherein a second output terminal of the shift register is electrically connected to a first terminal of the second switch,

wherein a third terminal of the first switch and a third terminal of the second switch are electrically connected to a wiring to which a first potential is input,

wherein a third terminal of the third switch is electrically connected to a common wiring,

wherein a first signal generated from a signal of the second input signal line is output to the output signal line,

wherein when a potential of the second input signal line is L, the first terminal of the first switch and the second terminal of the first switch are electrically connected to each other, the first terminal of the second switch and the second terminal of the second switch are electrically connected to each other, and the second terminal of the third switch and the third terminal of the third switch are electrically connected to each other, and

wherein when the potential of the second input signal line is H, the second terminal of the first switch and the third terminal of the first switch are electrically connected to each other, the second terminal of the second switch and the third terminal of the second switch are electrically connected to each other, and the first terminal of the third switch and the second terminal of the third switch are electrically connected to each other.

2 . The semiconductor device according to claim 1 , further comprising a fourth switch and a fourth buffer,

wherein a first terminal of the fourth switch is electrically connected to a third output terminal of the shift register, a second terminal of the fourth switch is electrically connected to a third scan line through the fourth buffer, and a third terminal of the fourth switch is electrically connected to the wiring to which the first potential is input.

3 . The semiconductor device according to claim 1 , further comprising a pixel,

wherein the pixel comprises a first display element, and

wherein the first display element is a transmissive liquid crystal element.

4 . The semiconductor device according to claim 3 ,

wherein the pixel comprises the first display element and a second display element,

wherein the first display element is configured to reflect visible light, and

wherein the second display element is configured to emit visible light.

5 . The semiconductor device according to claim 4 , wherein the second display element is a light-emitting element.

6 . A semiconductor device comprising a gate driver,

wherein the gate driver includes a decoder, a selection circuit, a first buffer, and a third buffer,

wherein the selection circuit is electrically connected to a first input signal line,

wherein the selection circuit comprises a shift register, a first switch, and a third switch,

wherein a second terminal of the first switch is electrically connected to a first scan line through the first buffer,

wherein a second terminal of the third switch is electrically connected to a touch wiring through the third buffer,

wherein the decoder is electrically connected to the first input signal line, a second input signal line, and an output signal line,

wherein the output signal line is electrically connected to an input terminal of the shift register and to a first terminal of the third switch,

wherein a first output terminal of the shift register is electrically connected to a first terminal of the first switch,

wherein a third terminal of the first switch is electrically connected to a wiring to which a first potential is input,

wherein a third terminal of the third switch is electrically connected to a common wiring,

wherein a first signal generated from a signal of the second input signal line is output to the output signal line,

wherein when a potential of the second input signal line is L, the first terminal of the first switch and the second terminal of the first switch are electrically connected to each other and the second terminal of the third switch and the third terminal of the third switch are electrically connected to each other, and

wherein when the potential of the second input signal line is H, the second terminal of the first switch and the third terminal of the first switch are electrically connected to each other and the first terminal of the third switch and the second terminal of the third switch are electrically connected to each other.

7 . The semiconductor device according to claim 6 , further comprising a pixel,

wherein the pixel comprises a first display element, and

wherein the first display element is a transmissive liquid crystal element.

8 . The semiconductor device according to claim 7 ,

wherein the pixel comprises the first display element and a second display element,

wherein the first display element is configured to reflect visible light, and

wherein the second display element is configured to emit visible light.

9 . The semiconductor device according to claim 8 , wherein the second display element is a light-emitting element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2025
From: MIYAKE, HIROYUKI; FUKUTOME, TAKAHIRO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 069879/0251 →
Continuity (4)
Continuation 18184803 · Mar 16, 2023
Continuation 17335186 · Jun 1, 2021
Continuation 15784550 · Oct 16, 2017
Related Publication 20250156002A1 · May 15, 2025
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