Memory system and method of controlling nonvolatile memory
According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
1 . A memory system connectable to a host, the host including a write buffer and a submission queue, the memory system comprising:
a nonvolatile memory including a plurality of blocks that includes at least a first block, each of the plurality of blocks being a unit of a data erase operation, a minimum data size of a data write operation to the nonvolatile memory being a first size; and
a controller electrically connected to the nonvolatile memory and configured to:
fetch a first write command from the submission queue of the host, the first write command requesting to write first write data to the nonvolatile memory, the first write data being associated with a first logical address and having a second size smaller than the first size;
determine that a write destination of the first write data is within the first block; and
update an address translation table such that the first logical address is mapped to at least the first block, wherein
the controller is configured to start the updating of the address translation table for the first logical address before obtaining the first write data from the write buffer of the host is finished, in response to determining that the second size is smaller than the first size.
2 . The memory system of claim 1 , wherein
the controller is further configured to:
fetch a second write command from the submission queue of the host, the second write command requesting to write second write data to the nonvolatile memory, the second write data being associated with a second logical address and having a third size;
determine that a write destination of the second write data is within the first block;
update the address translation table such that the second logical address is mapped to at least the first block; and
in response to determining that a total of the second size and the third size is larger than or equal to the first size,
obtain third write data from the write buffer of the host, the third write data having the first size and including at least part of the first write data and at least part of the second write data; and
write the third write data to the first block, wherein
the controller is configured to start the updating of the address translation table for the second logical address before the obtaining of the third write data is finished or before the writing of the third write data to the first block is finished.
3 . The memory system of claim 2 , wherein
the first write command and the second write command specify a same identifier, and
the controller is configured to determine that the total of the second size and the third size is larger than or equal to the first size, based on the first write command and the second write command specifying the same identifier.
4 . The memory system of claim 2 , wherein
each of write commands stored in the submission queue of the host specifies an stream identifier, the write commands including at least the first write command and the second write command, and
the controller is further configured to:
determine, per stream identifier, whether a total of data sizes specified by at least two of the write commands is larger than or equal to the first size.
5 . The memory system of claim 4 , further comprising:
a plurality of queues, wherein
the controller is further configured to:
store, per stream identifier, write commands fetched from the submission queue of the host in one of the plurality of queues; and
determine, per stream identifier, the total of data sizes specified by the at least two of the write commands stored in the one of the plurality of queues.
6 . The memory system of claim 2 , wherein
the controller is further configured to return a response indicative of completion of the first write command to the host when the updating of the address translation table for the first logical address is finished and when the obtaining of the third write data is finished, or when the updating of the address translation table for the first logical address is finished and when the writing of the third write data to the first block is finished.
7 . The memory system of claim 1 , wherein
the controller is further configured to return a response indicating that the first write command is received to the host when the updating of the address translation table for the first logical address is finished.
8 . The memory system of claim 1 , wherein
the controller is further configured to:
in response to determining that a time period elapsed since fetching the first write command exceeds a first threshold, obtain the first write data from the write buffer of the host even when the second size is smaller than the first size.
9 . The memory system of claim 1 , wherein
the controller is further configured to:
after updating the address translation table for the first logical address and before obtaining the first write data from the write buffer of the host, fetch a first read command from the submission queue of the host, the first read command specifying the first logical address; and
in response to the fetched first read command,
obtain the first write data from the write buffer of the host; and
transfer the obtained first write data to the host.
10 . The memory system of claim 1 , wherein
each of the plurality of blocks includes a plurality of pages, and
the first size is an integer multiple of a size of each of the plurality of pages.
11 . A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of blocks that includes at least a first block, each of the plurality of blocks being a unit of a data erase operation, a minimum data size of a data write operation to the nonvolatile memory being a first size, the method comprising:
fetching a first write command from a submission queue of a host, the first write command requesting to write first write data to the nonvolatile memory, the first write data being associated with a first logical address and having a second size smaller than the first size;
determining that a write destination of the first write data is within the first block;
determining that the second size is smaller than the first size; and
updating an address translation table such that the first logical address is mapped to at least the first block, wherein
the updating of the address translation table for the first logical address is started before obtaining the first write data from a write buffer of the host is finished, in response to determining that the second size is smaller than the first size.
12 . The method of claim 11 , further comprising:
fetching a second write command from the submission queue of the host, the second write command requesting to write second write data to the nonvolatile memory, the second write data being associated with a second logical address and having a third size;
determining that a write destination of the second write data is within the first block;
updating the address translation table such that the second logical address is mapped to at least the first block;
determining that a total of the second size and the third size is larger than or equal to the first size; and
in response to determining that the total of the second size and the third size is larger than or equal to the first size,
obtaining third write data from the write buffer of the host, the third write data having the first size and including at least part of the first write data and at least part of the second write data; and
writing the third write data to the first block, wherein
the updating of the address translation table for the second logical address is started before the obtaining of the third write data is finished or before the writing of the third write data to the first block is finished.
13 . The method of claim 12 , wherein
the first write command and the second write command specify a same identifier, and
the total of the second size and the third size is determined to be larger than or equal to the first size, based on the first write command and the second write command specifying the same identifier.
14 . The method of claim 12 , wherein
each of write commands stored in the submission queue of the host specifies an stream identifier, the write commands including at least the first write command and the second write command, and
the method further comprises:
determining, per stream identifier, whether a total of data sizes specified by at least two of the write commands is larger than or equal to the first size.
15 . The method of claim 14 , further comprising:
storing, per stream identifier, write commands fetched from the submission queue of the host in one of a plurality of queues; and
determining, per stream identifier, the total of data sizes specified by the at least two of the write commands stored in the one of the plurality of queues.
16 . The method of claim 12 , further comprising:
returning a response indicative of completion of the first write command to the host when the updating of the address translation table for the first logical address is finished and when the obtaining of the third write data is finished, or when the updating of the address translation table for the first logical address is finished and when the writing of the third write data to the first block is finished.
17 . The method of claim 11 , further comprising:
returning a response indicating that the first write command is received to the host when the updating of the address translation table for the first logical address is finished.
18 . The method of claim 11 , further comprising:
determining that a time period elapsed since fetching the first write command exceeds a first threshold; and
in response to determining that the time period exceeds the first threshold, obtaining the first write data from the write buffer of the host even when the second size is smaller than the first size.
19 . The method of claim 11 , further comprising:
after updating the address translation table for the first logical address and before obtaining the first write data from the write buffer of the host, fetching a first read command from the submission queue of the host, the first read command specifying the first logical address; and
in response to the fetched first read command,
obtaining the first write data from the write buffer of the host; and
transferring the obtained first write data to the host.
20 . The method of claim 11 , wherein
each of the plurality of blocks includes a plurality of pages, and
the first size is an integer multiple of a size of each of the plurality of pages.