Apparatuses, methods, and systems for hardware control of processor performance levels
Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
1 . A processor, comprising:
a plurality of cores, each core comprising a plurality of logical processing elements; and
power management circuitry including a plurality of registers, wherein the power management circuitry is to:
set to default values, during a boot time, a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, wherein the highest non-guaranteed performance level is greater than the highest guaranteed performance level for each of the plurality of logical processing elements;
process a request from an operating system to change the default value of the highest non-guaranteed performance level for a particular logical processing element of the plurality of logical processing elements to a new value; and
store a notification in a register of the plurality of registers to indicate to the operating system a result corresponding to the request.
2 . The processor of claim 1 wherein the notification is to subsequently be cleared by the operating system.
3 . The processor of claim 1 wherein the plurality of registers include a plurality of capabilities registers, each logical processing element associated with a different set of the plurality of capabilities registers, wherein a capabilities register associated with the particular logical processing element is to store the new value of the highest non-guaranteed performance level.
4 . The processor of claim 1 , wherein the request comprises a first request, the power management circuitry to process a second request from the operating system to read the highest non-guaranteed performance level for the particular logical processing element of the plurality of logical processing elements.
5 . The processor of claim 1 , wherein the power management circuitry is to set a bit in at least one of the plurality of registers in response to an excursion of the particular logical processing element to a performance level below an indicated minimum performance level.
6 . The processor of claim 5 , wherein the bit is to be subsequently cleared by the operating system.
7 . The processor of claim 1 , wherein storing the notification in the register is to cause the operating system to read the new highest non-guaranteed performance level from a capabilities register.
8 . The processor of claim 1 , wherein the new value of the highest non-guaranteed performance level is greater than the default highest non-guaranteed performance level.
9 . The processor of claim 1 , wherein storing the notification in the register is to cause an interrupt to be generated.
10 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a processor, causes the processor to perform operations comprising:
during a boot time, cause power management circuitry to set to default values a highest non-guaranteed performance level and a highest guaranteed performance level for each of a plurality of logical processing elements, wherein the highest non-guaranteed performance level is greater than the highest guaranteed performance level for each of the plurality of logical processing elements;
submit a request from an operating system to change the default value of the highest non-guaranteed performance level for a particular logical processing element of the plurality of logical processing elements to a new value; and
read a notification in a register of a plurality of registers, the notification to indicate to the operating system a result corresponding to the request; and
subsequently clear the notification responsive to the operating system.
11 . The non-transitory machine-readable medium of claim 10 wherein the register comprises one of a plurality of registers of the power management circuitry, the plurality of registers including a plurality of capabilities registers, each logical processing element associated with a different set of the plurality of capabilities registers, wherein a capabilities register associated with the particular logical processing element is to store the new value of the highest non-guaranteed performance level.
12 . The non-transitory machine-readable medium of claim 10 , wherein the request comprises a first request, the non-transitory machine-readable medium including additional program code to cause the processor to: submit a second request from the operating system to read the highest non-guaranteed performance level for the particular logical processing element of the plurality of logical processing elements.
13 . The non-transitory machine-readable medium of claim 10 , wherein the power management circuitry is to set a bit in at least one of the plurality of registers in response to an excursion of the particular logical processing element to a performance level below an indicated minimum performance level, the non-transitory machine-readable medium including additional program code to cause the processor to: subsequently clear the bit responsive to the operating system.
14 . The non-transitory machine-readable medium of claim 10 , wherein the new value of the highest non-guaranteed performance level is greater than the default highest non-guaranteed performance level.
15 . The non-transitory machine-readable medium of claim 10 including additional program code to cause the processor to: causing an interrupt to be generated responsive to the notification.