Semiconductor memory device with spin-orbit coupling channel
A semiconductor memory device may be provided. The semiconductor memory device may include data storage patterns having respective first sides and respective second sides, a spin-orbit coupling (SOC) channel layer in common contact with the first sides of the data storage patterns, the SOC channel layer is configured to provide a spin-orbit torque to the data storage patterns, read access transistors connected between the second sides of respective ones of the data storage patterns and respective data lines, a write access transistor connected between a first end of the SOC channel layer and a source line, and a bit line connected to a second end of the SOC channel layer. Each of the data storage patterns comprises a free layer in contact with the SOC channel layer and an oxygen reservoir layer in contact with the free layer.
1 . A semiconductor memory device, comprising: a spin-orbit coupling (SOC) channel layer;
a plurality of data storage patterns on the SOC channel layer,
each of the data storage patterns comprising a free layer in contact with the SOC channel layer,
a fixed layer on the free layer, an oxygen reservoir layer between the free layer and the fixed layer,
a first tunnel magnetoresistance (TMR) enhancement layer between the free layer and the oxygen reservoir layer, and
a second TMR enhancement layer between the oxygen reservoir layer and the fixed layer;
a write access transistor connected between a first end of the SOC channel layer and a source line; and
read access transistors respectively connected between respective ones of the fixed layers of the data storage patterns and respective data lines,
wherein the SOC channel layer is configured to provide a spin-orbit torque to the data storage patterns, and
wherein each of the data storage patterns is configured such that an amount of oxygen in an interface region between the free layer and the SOC channel layer is adjusted by a voltage applied thereto.
2 . The semiconductor memory device of claim 1 , wherein the oxygen reservoir layer comprises a rare-earth element.
3 . The semiconductor memory device of claim 1 , wherein the oxygen reservoir layer comprises a gadolinium oxide (GdOx) layer.
4 . The semiconductor memory device of claim 3 , wherein the gadolinium oxide layer has a thickness of 3 nm to 20 nm.
5 . The semiconductor memory device of claim 1 , wherein the SOC channel layer comprises a platinum layer (Pt) having a thickness of 1 nm to 2.5 nm.
6 . The semiconductor memory device of claim 1 , wherein the oxygen reservoir layer comprises an oxide material configured to cause migration of an oxygen ion when a voltage is applied thereto.
7 . A semiconductor memory device, comprising: a bit line and a source line;
a plurality of sub-arrays, which are respectively connected between the bit line and the source line, each of the sub-arrays comprising a plurality of data storage devices, a plurality of read access transistors connected to the data storage devices,
a spin-orbit coupling (SOC) channel layer connected in common to the data storage devices, and a write access transistor connected to a first end of the SOC channel layer;
write word lines in respective ones of the sub-arrays,
wherein each of the write word lines is connected to a gate electrode of the write access transistor of a respective one of the sub-arrays;
read word lines in respective ones of the sub-arrays,
wherein each of the read word lines of a respective sub-array is connected in common to gate electrodes of the read access transistors of the respective sub-array; and
data lines connected to ones of the read access transistors of each of the plurality of sub-arrays of the semiconductor memory device,
wherein each of the data storage devices comprises a free layer in contact with the SOC channel layer and an oxygen reservoir layer on the free layer.
8 . The semiconductor memory device of claim 7 , wherein the semiconductor memory device is configured to migrate oxygen ions towards an interface between the SOC channel layer and the free layer when a first voltage is applied to the gate electrode and is configured to migrate oxygen ions towards an interface between the oxygen reservoir layer and the free layer when a second voltage that is opposite in polarity to the first voltage is applied to the gate electrode.
9 . The semiconductor memory device of claim 7 , wherein the oxygen reservoir layer comprises a gadolinium oxide (GdOx) layer.
10 . The semiconductor memory device of claim 7 , wherein a thickness of the oxygen reservoir layer is greater than a thickness of the SOC channel layer or a thickness of the free layer.