Nonvolatile memory device including wordline leakage current detector, storage device including the same, and method of operating the same
A nonvolatile memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a row decoder configured to select one of the plurality of wordlines in response to an address, and a wordline leakage current detector configured to determine whether the selected wordline is defective using trim information related to a level of a reference voltage or a gradient of a detect voltage during a test operation, wherein the trim information is stored internally in an electrical die sorting (EDS) process.
1 . A nonvolatile memory device, comprising:
a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines;
a row decoder configured to select one of the plurality of wordlines in response to an address; and
a wordline leakage current detector configured to determine whether the selected wordline is defective using trim information related to a level of a reference voltage or a gradient of a detect voltage during a test operation,
wherein the trim information is stored internally in an electrical die sorting (EDS) process.
2 . The nonvolatile memory device of claim 1 ,
wherein the memory cell array and the row decoder include a core chip and a peripheral chip disposed below the core chip, and
wherein the peripheral chip includes the wordline leakage current detector.
3 . The nonvolatile memory device of claim 1 , wherein first trim information related to a level of the reference voltage is extracted from the EDS process and stored in an E-fuse for each chip.
4 . The nonvolatile memory device of claim 3 , wherein the first trim information is determined by starting a detecting operation of the wordline leakage current detector from a level corresponding to a default value in the EDS process, and repeating the detecting operation while lowering a level by a predetermined level until the detecting operation passes.
5 . The nonvolatile memory device of claim 3 , wherein the wordline leakage current detector compares a detected voltage of the selected wordline with a reference voltage corresponding to the first trim information in the test operation, and outputs a good product signal corresponding to a result of the comparison.
6 . The nonvolatile memory device of claim 3 , wherein the wordline leakage current detector includes:
a first capacitor connected between a first node and a second node providing a test voltage to the selected wordline during the test operation;
a second capacitor connected between the second node and a ground terminal;
a comparator configured to compare the detected voltage with a reference voltage of the second node and to output a good product signal corresponding to a result of the comparison; and
a reference voltage generator configured to generate the reference voltage using the first trim information.
7 . The nonvolatile memory device of claim 1 , wherein second trim information related to a gradient of the detected voltage is extracted from the EDS process and stored in an E-fuse for each chip.
8 . The nonvolatile memory device of claim 7 , wherein the second trim information corresponds to a difference between a first count value at which the detected voltage reaches a first level and a second count value at which the detected voltage reaches a second level in the EDS process.
9 . The nonvolatile memory device of claim 7 , wherein the wordline leakage current detector includes:
a first comparator configured to compare a corresponding detected voltage with a first reference voltage and to output a first output voltage when applying a test voltage to the selected wordline in the test operation;
a second comparator configured to compare the detected voltage with a second reference voltage different from the first reference voltage and to output a second output voltage;
a first counter configured to output a first count value by counting until the first output voltage reaches a first level;
a second counter configured to output a second count value by counting until the second output voltage reaches a second level different from the first level;
a first register configured to store the first count value;
a second register configured to store the second count value;
a calculation unit configured to calculate a difference value between the first count value and the second count value; and
a verification comparator configured to compare the difference value with a count value corresponding to the second trim information and to output a good product signal corresponding to a result of the comparison.
10 . The nonvolatile memory device of claim 9 , wherein the wordline leakage current detector further includes a fuse trim set configured to output the second reference voltage by trimming the first reference voltage.
11 . A method of operating a nonvolatile memory device including a core chip having memory blocks connected to wordlines and bitlines and a peripheral chip disposed below the core chip and having a wordline leakage current detector, the method comprising:
extracting trim information related to a level of a reference voltage of the wordline leakage current detector or a gradient of detected voltage of the wordline leakage current detector for each chip in an electrical die sorting (EDS) process; and
testing leakage of a target wordline among the wordlines in a test operation using the trim information.
12 . The method of claim 11 , wherein the extracting the trim information includes:
determining whether a detecting operation of the wordline leakage current detector passes at a reference level corresponding to a default value;
determining whether a detecting operation of the wordline leakage current detector passes while lowering the reference level to a predetermined level.
13 . The method of claim 11 , wherein the extracting trim information includes:
outputting a first count value until the detected voltage reaches a first reference voltage;
outputting a second count value until the detected voltage reaches a second reference voltage different from the first reference voltage; and
storing the trim information corresponding to a difference value between the second count value and the first count value.
14 . The method of claim 13 , wherein the testing leakage of a target wordline includes:
calculating a difference value between a count value at which the detected voltage reaches the first reference voltage and a count value at which the detected voltage reaches the second reference voltage in the test operation; and
outputting a good product signal configured to determine leakage of the target wordline by comparing the calculated difference value with a count value corresponding to the trim information.
15 . The method of claim 11 , wherein the wordline leakage current detector is shared by at least two planes.
16 . A storage device, comprising:
at least one nonvolatile memory device; and
a controller configured to control the at least one nonvolatile memory device,
wherein the at least one nonvolatile memory device includes:
a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines; and
a wordline leakage current detector configured to determine whether the selected wordline among the plurality of wordlines is defective using trim information related to a level of a reference voltage or a gradient of detected voltage during a test operation.
17 . The storage device of claim 16 , wherein the trim information is extracted for each chip in an electrical die sorting (EDS) process and stored in the at least one nonvolatile memory device.
18 . The storage device of claim 16 , wherein the test operation is performed according to a request from the controller or an internal policy.
19 . The storage device of claim 16 , wherein the wordline leakage current detector compares a detected voltage of the selected wordline with a reference voltage corresponding to the trim information in the test operation, and outputs a good product signal corresponding to a result of the comparison.
20 . The storage device of claim 16 , wherein the wordline leakage current detector calculates a difference value between a first count value at which the detected voltage reaches a first level and a second count value at which the detected voltage reaches a second level different from the first level in the test operation, compares a difference value with a count value corresponding to the trim information, and outputs a good product signal corresponding to a result of the comparison.