Granted Patent B2

US 12,549,003 · App. 18/130,928 · Granted Feb 10, 2026

Inventors: David Salvo Lillo (Lliria, ES); Abelardo Salvo Lillo (Lliria, ES); Josué Juan Aguilar (Lliria, ES); Jose Luis Camps Soriano (Lliria, ES)

Assignee: Power Electronics España, S.L.

H02J1/102H02J3/32H02J2300/24

Abstract

Claims (38)

1 . An intrinsic biasing method for a dual DC/DC converter,

wherein the dual DC/DC converter comprises:

an internal bus on a photovoltaic solar field side which in turn comprises:

a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series;

resistors and capacitors connected in series;

wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the photovoltaic solar field side is connectable to a photovoltaic solar field by means of second closure means;

an internal bus on a battery side which in turn comprises:

a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series;

resistors and capacitors connected in series;

wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the battery side is connectable to a battery rack by means of first closure means;

wherein the method comprises the following steps:

i) connecting the dual DC/DC converter with the photovoltaic solar field by closing the second closure means and isolating the dual DC/DC converter from the battery rack by opening the first closure means;

ii) pre-charging the internal bus on the battery side at the same voltage with respect to ground that the battery rack has with energy from the photovoltaic solar field by means of predefined switching of the transistors of the battery side and the transistors of the photovoltaic solar field side;

iii) isolating the internal bus on the battery side from the internal bus on the photovoltaic solar field side until the internal bus on the battery side is biased equal to the battery rack, leaving the transistors of the internal bus on the photovoltaic solar field side open;

iv) connecting the internal bus on the battery side with the battery rack, closing the first closure means;

v) opening the first transistor, the fourth transistor, the fifth transistor and the eighth transistor;

vi) biasing the internal bus on the battery side at a voltage with respect to ground by means of synchronized switching of the second transistor, the third transistor, the sixth transistor and the seventh transistor, wherein the synchronized switching of the transistors is carried out in periods of time “T” with increasing duty cycles in time increments from a minimum value equivalent to a switching time of the second transistor, the third transistor, the sixth transistor and the seventh transistor to a maximum value where the second transistor, the third transistor, the sixth transistor and the seventh transistor are closed.

2 . The method of claim 1 , wherein the step ii) additionally comprises the dual DC/DC converter working as a “buck” type converter when a voltage in the battery rack is lower than a voltage in the photovoltaic solar field.

3 . The method of claim 1 , wherein the step ii) additionally comprises the dual DC/DC converter working as a “boost” type converter when a voltage in the battery rack is higher than a voltage in the photovoltaic solar field.

4 . The method of claim 2 , wherein the step ii) additionally comprises:

opening the sixth transistor and the seventh transistor;

closing the fifth transistor and the eighth transistor;

switching the first transistor, the second transistor, the third transistor, and the fourth transistor.

5 . The method of claim 3 , wherein the step ii) additionally comprises:

opening the second transistor and the third transistor;

closing the first transistor and the fourth transistor;

switching the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor.

6 . A dual DC/DC converter comprising:

an internal bus on a photovoltaic solar field side which in turn comprises:

a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series;

resistors and capacitors connected in series;

wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the photovoltaic solar field side is connectable to a photovoltaic solar field by means of second closure means;

an internal bus on a battery side which in turn comprises:

a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series;

resistors and capacitors connected in series;

wherein the transistors connected in series are connected in parallel to the resistors and the capacitors connected in series; and wherein the internal bus on the battery side is connectable to a battery rack by means of first closure means;

wherein the dual DC/DC converter comprises control means connected to at least the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first closure means, the second closure means, wherein the control means are configured to carry out the intrinsic biasing method for the dual DC/DC converter defined in claim 1 .

7 . The dual DC/DC converter of claim 6 , wherein the control means are selected from among a microcontroller, a microprocessor and an FPGA.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (28)