Granted Patent B2

US 12,549,359 · App. 18/782,322 · Granted Feb 10, 2026

Inventor: Zong-Min Lin (Kaohsiung, TW)

Assignee: NUVOTON TECHNOLOGY CORPORATION

H04L9/0894G06F21/107G06F21/121

Abstract

Claims (75)

1 . A micro-controller comprising:

a secure world comprising:

a key management device storing a secret key;

a decryption circuit utilizing the secret key to decrypt an encrypted model to generate a decrypted model; and

a first memory storing the decrypted model;

a non-secure world comprising:

a second memory storing the encrypted model; and

a third memory storing an inference result; and

a processing circuit providing input data to the decrypted model,

wherein the decrypted model generates the inference result according to the input data,

wherein in a non-secure mode, the processing circuit reads the encrypted model stored in the second memory and calls a software function,

wherein the processing circuit provides addresses of the encrypted model, the input data and the inference result to the software function, and

wherein in a secure mode, the processing circuit executes the software function to:

direct the decryption circuit to read the secret key;

direct the decryption circuit to utilize the secret key to decrypt the encrypted model to generate the decrypted model; and

store the decrypted model in the first memory.

2 . The micro-controller as claimed in claim 1 , wherein the software function is stored in the secure world.

3 . The micro-controller as claimed in claim 1 , wherein the processing circuit enters the secure mode and executes the software function.

4 . The micro-controller as claimed in claim 1 , wherein in the secure mode, the processing circuit further executes the software function to:

execute the decrypted model to generate the inference result;

store the inference result in the third memory; and

enter the non-secure mode.

5 . The micro-controller as claimed in claim 1 , wherein the non-secure world further comprises:

a transmission interface configured to receive the encrypted model.

6 . The micro-controller as claimed in claim 5 , wherein the transmission interface is an internet interface.

7 . The micro-controller as claimed in claim 1 , wherein the second memory is a non-volatile memory, and each of the first and third memories is a volatile memory.

8 . The micro-controller as claimed in claim 1 , wherein the decrypted model is a neural network model.

9 . A secure system, comprising:

a micro-controller comprising:

a secure world comprising:

a key management device storing a secret key;

a decryption circuit utilizing the secret key to decrypt an encrypted model to generate a decrypted model; and

a first memory storing the decrypted model;

a non-secure world comprising:

a second memory storing the encrypted model; and

a third memory storing an inference result;

a processing circuit providing input data to the decrypted model, wherein the decrypted model generates the inference result according to the input data, and the processing circuit stores the inference result in the third memory; and

an offline tool comprising:

an encryption circuit utilizing the secret key to encrypt a network model to generate the encrypted model and storing the encrypted model in the second memory,

wherein in a non-secure mode, the processing circuit reads the encrypted model stored in the second memory and calls a software function,

wherein the processing circuit provides addresses of the encrypted model, the input data and the inference result to the software function, and

wherein in a secure mode, the processing circuit executes the software function to:

direct the decryption circuit to read the secret key;

direct the decryption circuit to utilize the secret key to decrypt the encrypted model to generate the decrypted model; and

store the decrypted model in the first memory.

10 . The secure system as claimed in claim 9 , wherein the encryption circuit utilizes the secret key to execute a symmetric encryption operation for the network model, and the decryption circuit utilizes the secret key to execute a symmetric decryption operation for the encrypted model.

11 . The secure system as claimed in claim 9 , wherein the offline tool further comprises:

a provision circuit provisioning the secret key to the key management device.

12 . The secure system as claimed in claim 9 , wherein the offline tool is independent of the micro-controller.

13 . A protection method applied in a processing circuit and comprising:

in a non-secure mode:

reading an encrypted model in a non-secure world;

calling a software function in a secure world; and

entering a secure mode; and

in the secure mode:

executing the software function to:

read a secret key in the secure world;

utilize the secret key to decrypt the encrypted model to generate a decrypted model; and

execute the decrypted model to generate an inference result,

wherein in the non-secure mode, the encrypted model is read and a software function is called,

wherein the method further comprising in the non-secure mode, providing addresses of the encrypted model, the input data and the inference result to the software function, and

wherein in the secure mode, executing the software function to:

direct the decryption circuit to read the secret key;

direct the decryption circuit to utilize the secret key to decrypt the encrypted model to generate the decrypted model; and

store the decrypted model in the first memory.

14 . The protection method as claimed in claim 13 , wherein the decrypted model is stored in the secure world.

15 . The protection method as claimed in claim 13 , further comprising:

in the secure mode:

storing the inference result in the non-secure world; and

in the non-secure mode:

reading the inference result in the non-secure world.

16 . The protection method as claimed in claim 13 , further comprising:

encrypting a network model to generate the encrypted model;

utilizing an internet to transmit the encrypted model to the non-secure world; and

provisioning the secret key to the secure world.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (9)