Transistor device having groups of transistor cells with different body region average doping concentrations and different source region densities
A transistor device includes: a plurality of transistor cells in a semiconductor substrate; and a source pad above the semiconductor substrate and electrically connected to a source region and a body region of the transistor cells. A first group of the transistor cells has a first body region average doping concentration. A second group of the transistor cells has a second body region average doping concentration higher than the first body region average doping concentration. The transistor cells of the first and second groups are interleaved. The transistor cells have a first source region density in a first area of the semiconductor substrate underneath a region of the source pad designated for clip contacting, and a second source region density lower than the first source region density in a second area of the semiconductor substrate outside the first area.
1 . A transistor device, comprising:
a plurality of transistor cells in a semiconductor substrate; and
a source pad above the semiconductor substrate and electrically connected to a source region and a body region of the transistor cells,
wherein a first group of the transistor cells has a first body region average doping concentration,
wherein a second group of the transistor cells has a second body region average doping concentration higher than the first body region average doping concentration,
wherein the transistor cells of the first and second groups are interleaved,
wherein the transistor cells have a first source region density in a first area of the semiconductor substrate underneath a region of the source pad designated for clip contacting, and a second source region density lower than the first source region density in a second area of the semiconductor substrate outside the first area.
2 . The transistor device of claim 1 , wherein the second group of the transistor cells provides a larger area of the body region than the first group of the transistor cells.
3 . The transistor device of claim 1 , wherein a third group of the transistor cells has a third body region average doping concentration higher than the second body region average doping concentration, and wherein the transistor cells of the first, second and third groups are interleaved.
4 . The transistor device of claim 3 , wherein the third group of the transistor cells provides a larger area of the body region than the second group of the transistor cells, and wherein the second group of the transistor cells provides a larger area of the body region than the first group of the transistor cells.
5 . The transistor device of claim 1 , wherein the source region of the transistor cells is segmented into stripes in the second area of the semiconductor substrate that are spaced apart from one another and run transverse to stripe-shape gate structures of the transistor cells.
6 . The transistor device of claim 5 , wherein the source region stripes in the second area of the semiconductor substrate are spaced apart from one another by a distance that corresponds to a width of the source region stripes in the second area of the semiconductor substrate.
7 . The transistor device of claim 1 , wherein the source region of the transistor cells has a graded density outside the first area of the semiconductor substrate and that increases heading towards the first area of the semiconductor substrate.
8 . The transistor device of claim 1 , wherein the source region of the transistor cells has a checkerboard pattern in the second area of the semiconductor substrate.
9 . The transistor device of claim 1 , wherein the first source region density is 50% or greater and the second source region density is less than 90%, and wherein with the second source region density is less than or equal to the first source region density.
10 . The transistor device of claim 1 , wherein the transistor cells have a third source region density in a third area of the semiconductor substrate outside the second area, and wherein the third source region density is lower than the second source region density.
11 . The transistor device of claim 10 , wherein the third area of the semiconductor substrate is outside an opening in a passivation layer that adjoins the source pad.
12 . The transistor device of claim 10 , wherein the source region of the transistor cells is segmented into stripes in the second area and the third area of the semiconductor substrate that are spaced apart from one another and run transverse to stripe-shape gate structures of the transistor cells.
13 . The transistor device of claim 12 , wherein the source region stripes in the third area of the semiconductor substrate have the same width as the source region stripes in the second area of the semiconductor substrate, and wherein the source region stripes in the third area of the semiconductor substrate are spaced apart from one another by a greater distance than the source region stripes in the second area of the semiconductor substrate.
14 . The transistor device of claim 12 , wherein the source region stripes in the second area of the semiconductor substrate are spaced apart from one another by a distance that corresponds to a width of the source region stripes in the second area of the semiconductor substrate, and wherein the source region stripes in the third area of the semiconductor substrate are spaced apart from one another by a distance that corresponds to twice a width of the source region stripes in the third area of the semiconductor substrate.
15 . The transistor device of claim 10 , wherein the first source region density is 50% or greater, the second source region density is greater than 33% and less 90%, and the third source region density is 33% or less, and wherein the third source region density is less than or equal to the second source region density and the second source region density is less than or equal to the first source region density.
16 . The transistor device of claim 1 , further comprising:
a metallic clip attached to the region of the source pad designated for clip contacting.
17 . A semiconductor device, comprising:
a transistor device formed in a semiconductor substrate;
a source pad above the semiconductor substrate and electrically connected to a source region and a body region of the transistor device; and
a metallic clip attached to a region of the source pad designated for clip contacting,
wherein the body region of the transistor device has interleaved zones of at least two different threshold voltages,
wherein the source region of the transistor device has a first density in a first area of the semiconductor substrate underneath the region of the source pad designated for clip contacting, and a second density lower than the first density in a second area of the semiconductor substrate outside the first area.
18 . The semiconductor device of claim 17 , wherein the body region of the transistor device has interleaved zones of at least three different threshold voltages.
19 . The semiconductor device of claim 17 , wherein the source region of the transistor device has a third density lower than the second density in a third area of the semiconductor substrate outside the second area.
20 . The semiconductor device of claim 19 , wherein the third area of the semiconductor substrate is outside an opening in a passivation layer that adjoins the source pad.
21 . A transistor device, comprising:
a plurality of transistor cells in a semiconductor substrate; and
a source pad above the semiconductor substrate and electrically connected to a source region and a body region of the transistor cells,
wherein a first group of the transistor cells has a first body region average doping concentration,
wherein a second group of the transistor cells has a second body region average doping concentration higher than the first body region average doping concentration,
wherein the transistor cells of the first and second groups are interleaved,
wherein the transistor cells have a first source region density in a first area of the semiconductor substrate and a second source region density lower than the first source region density in a second area of the semiconductor substrate outside the first area.