ESD protection circuit having different discharging paths
The present invention provides an ESD protection circuit including a control circuit, a first transistor, a filter and a second transistor. The control circuit is configured to detect a level of a supply voltage to generate a control signal. The first transistor is coupled between the supply voltage and a ground voltage, and is used to refer to the control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage. The filter is configured to filter the control signal to generate a filtered control signal. The second transistor is coupled between the supply voltage and the ground voltage, and is used to refer to the filtered control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage.
1 . An electrostatic discharge (ESD) protection circuit, comprising:
a control circuit, configured to detect a level of a supply voltage to generate a control signal;
a first transistor, coupled between the supply voltage and a ground voltage, configured to refer to the control signal to determine whether to be enabled as a first discharging path for the supply voltage to discharge current to the ground voltage;
a first filter, configured to filter the control signal to generate a first filtered control signal; and
a second transistor, coupled between the supply voltage and the ground voltage, configured to refer to the first filtered control signal to determine whether to be enabled as a second discharging path for the supply voltage to discharge current to the ground voltage.
2 . The ESD protection circuit of claim 1 , wherein a size of the second transistor is greater than a size of the first transistor.
3 . The ESD protection circuit of claim 1 , wherein an allowable maximum current of the second transistor is greater than an allowable maximum current of the first transistor.
4 . The ESD protection circuit of claim 1 , wherein the first filter is a low-pass filter with adjustable cutoff frequency.
5 . The ESD protection circuit of claim 1 , further comprising:
a second filter, configured to filter the first filtered control signal to generate a second filtered control signal; and
a third transistor, coupled between the supply voltage and the ground voltage, configured to refer to the first filtered control signal to determine whether to be enabled as a third discharging path for the supply voltage to discharge current to the ground voltage.
6 . The ESD protection circuit of claim 5 , wherein a size of the second transistor is greater than a size of the first transistor, and a size of the third transistor is greater than the size of the second transistor.
7 . The ESD protection circuit of claim 5 , wherein an allowable maximum current of the second transistor is greater than an allowable maximum current of the first transistor, and an allowable maximum current of the third transistor is greater than the allowable maximum current of the second transistor.
8 . The ESD protection circuit of claim 5 , wherein each of the first filter and the second filter is a low-pass filter with adjustable cutoff frequency.
9 . The ESD protection circuit of claim 1 , wherein the control circuit detects if the level of the supply voltage is greater than a threshold value to generate the control signal; and if the level of the supply voltage is greater than the threshold value, the control circuit generates the control signal to enable the first transistor.
10 . The ESD protection circuit of claim 9 , wherein the control circuit comprises:
a resistor, coupled between the supply voltage and a node;
a capacitor, coupled between the node and the ground voltage; and
an inverter, wherein the inverter is powered by the supply voltage, and the node is used as an input terminal of the inverter, and an output terminal of the inverter is used to generate the control signal.