Semiconductor package
A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.
1 . A semiconductor package comprising:
a first redistribution structure comprising a plurality of first redistribution layers and a plurality of first redistribution vias;
a semiconductor chip on the first redistribution structure, the semiconductor chip comprising a chip pad;
a connection pad between the first redistribution structure and the semiconductor chip, the connection pad connected to the first redistribution structure;
a connection bump connected to the connection pad and the chip pad;
a molding layer extending around the first redistribution structure and the semiconductor chip;
a through electrode extending through the molding layer; and
a wetting layer between the first redistribution structure and the molding layer, wherein the wetting layer defines a first opening and a second opening, wherein the through electrode is arranged in the first opening and the connection pad is arranged in the second opening.
2 . The semiconductor package of claim 1 , wherein an upper surface of the wetting layer is not coplanar with an upper surface of the connection pad, and wherein a lower surface of the wetting layer is coplanar with a lower surface of the connection pad.
3 . The semiconductor package of claim 1 , wherein an upper surface of the wetting layer is coplanar with an upper surface of the connection pad.
4 . The semiconductor package of claim 1 , wherein the wetting layer is spaced apart from the through electrode and the connection pad.
5 . The semiconductor package of claim 1 , wherein the wetting layer comprises any one of TaN, Ta, SiO, and SiN.
6 . The semiconductor package of claim 1 , further comprising a metal layer between the connection bump and the connection pad, wherein the metal layer is on an upper surface and side surfaces of the connection pad.
7 . The semiconductor package of claim 6 , wherein the wetting layer is spaced apart from the metal layer.
8 . The semiconductor package of claim 6 , wherein the metal layer comprises any one of Ni, Au, and an alloy thereof.
9 . The semiconductor package of claim 1 , wherein the connection pad and the through electrode comprise a same material.
10 . The semiconductor package of claim 1 , wherein the through electrode extends from an upper surface of the molding layer to a lower surface of the molding layer, and wherein a lower surface of the through electrode contacts an upper surface of the first redistribution via.
11 . A semiconductor package comprising:
a first redistribution structure comprising a plurality of first redistribution layers and a plurality of first redistribution vias;
a semiconductor chip on the first redistribution structure, the semiconductor chip comprising a chip pad;
a connection pad between the first redistribution structure and the semiconductor chip, the connection pad connected to the first redistribution structure;
a connection bump connected to the connection pad and the chip pad;
a molding layer extending around the first redistribution structure and the semiconductor chip;
a through electrode extending through the molding layer;
a wetting layer between the first redistribution structure and the molding layer; and
a second redistribution structure on the molding layer, the second redistribution structure comprising second redistribution layers and second redistribution vias,
wherein a width of each first redistribution via increases from an upper surface of the first redistribution via toward a lower surface of the first redistribution via, and wherein a width of each second redistribution via decreases from an upper surface of the second redistribution via toward a lower surface of the second redistribution via.
12 . The semiconductor package of claim 11 , further comprising a metal layer between the connection bump and the connection pad, wherein the metal layer is on an upper surface and side surfaces of the connection pad.
13 . The semiconductor package of claim 11 , wherein an upper surface of the wetting layer is not coplanar with an upper surface of the connection pad, and wherein a lower surface of the wetting layer is coplanar with a lower surface of the through electrode.
14 . The semiconductor package of claim 11 , wherein the wetting layer is spaced apart from the through electrode and the connection pad, and wherein a separation distance between the wetting layer and the through electrode is identical to a separation distance between the wetting layer and the connection pad.
15 . The semiconductor package of claim 11 , wherein the connection pad and the through electrode comprise a same material.
16 . The semiconductor package of claim 11 , wherein the through electrode extends from an upper surface of the molding layer to a lower surface of the molding layer, and wherein a lower surface of the through electrode is coplanar with the upper surface of the first redistribution via.
17 . A semiconductor package comprising:
a first redistribution structure comprising a plurality of first redistribution layers and a plurality of first redistribution vias;
a semiconductor chip on the first redistribution structure, the semiconductor chip comprising a chip pad;
a connection pad between the first redistribution structure and the semiconductor chip, the connection pad connected to the first redistribution structure;
a metal layer on an upper surface and side surfaces of the connection pad;
a connection bump connected to the metal layer and the semiconductor chip;
a molding layer extending around the first redistribution structure and the semiconductor chip;
a second redistribution structure on the molding layer, the second redistribution structure comprising second redistribution layers and second redistribution vias,
a wetting layer between the first redistribution structure and the molding layer; and
a through electrode extending through the molding layer, wherein the through electrode is connected to the first redistribution via and to the second redistribution via, and wherein the through electrode has a uniform width,
wherein a width of each first redistribution via increases from an upper surface of the first redistribution via toward a lower surface of the first redistribution via, and wherein a width of each second redistribution via decreases from an upper surface of the second redistribution via toward a lower surface of the second redistribution via.
18 . The semiconductor package of claim 17 , wherein an upper surface of the wetting layer is not coplanar with the upper surface of the first redistribution via.
19 . The semiconductor package of claim 17 , wherein the connection pad and the through electrode comprise copper (Cu).
20 . The semiconductor package of claim 17 , wherein the wetting layer is spaced apart from the through electrode and the metal layer, and wherein a separation distance between the wetting layer and the through electrode is identical to a separation distance between the wetting layer and the metal layer.