Clock glitch detector
View Patent ↗Embodiments herein describe a glitch detector circuit (and method of operation) for detecting glitches in a clock signal. In one embodiment, the glitch detector includes a shift register that samples the reference clock using a clock signal output by a PLL. The value in a first memory element of the shift register can be sampled to previous values that were stored (and then bit shifted) in the shift register. If there is a mismatch, the glitch detector indicates there was a clock glitch in the reference clock, and a corrective action can be performed.
1 . A clock glitch detector circuit comprising:
a phase locked loop (PLL) configured to generate a clock signal based on a reference clock;
a shift register configured to store a current value of the reference clock based on the clock signal;
a first set of latches configured to retrieve a plurality of shifted bits from the shift register;
a second set of latches configured to compare a bit value stored at a first memory element of the shift register to outputs of the first set of latches; and
OR logic coupled to the outputs of the second set of latches, wherein an output of the OR logic indicates whether there was a clock glitch.
2 . The clock glitch detector circuit of claim 1 , wherein the clock signal serves as a clock for the first set of latches.
3 . The clock glitch detector circuit of claim 1 , wherein the outputs of the first set of latches serve as clock signals for the second set of latches.
4 . The clock glitch detector circuit of claim 1 , wherein half of the second set of latches invert the bit value stored at the first memory element at their inputs.
5 . The clock glitch detector circuit of claim 1 , wherein the clock signal has a frequency that is a multiple of a frequency of the reference clock.
6 . The clock glitch detector circuit of claim 5 , wherein a number of the plurality of shifted bits retrieved by the first set of latches is equal to the multiple.
7 . An integrated circuit (IC), comprising:
a clock glitch detector comprising:
a shift register configured to store a current value of a reference clock based on a first clock signal,
a first set of latches configured to retrieve a plurality of shifted bits from the shift register,
a second set of latches configured to compare a bit value stored at a first memory element of the shift register to outputs of the first set of latches, and
OR logic coupled to the outputs of the second set of latches, wherein an output of the OR logic indicates whether there was a clock glitch; and
a phase-locked loop (PLL) configured to generate a second clock signal based on a third clock signal provided by the clock glitch detector.
8 . The IC of claim 7 , wherein the first clock signal serves as a clock for the first set of latches.
9 . The IC of claim 7 , wherein the outputs of the first set of latches serve as clock signals for the second set of latches.
10 . The IC of claim 7 , wherein half of the second set of latches invert the bit value stored at the first memory element at their inputs.
11 . The IC of claim 7 , wherein the first clock signal has a frequency that is a multiple of a frequency of the reference clock.
12 . The IC of claim 11 , wherein a number of the plurality of shifted bits retrieved by the first set of latches is equal to the multiple.
13 . The IC of claim 7 , further comprising:
an interface configured to couple the PLL to an external clock source, wherein the external clock source is configured to generate the reference clock.
14 . The IC of claim 7 , further comprising:
a clock source configured to generate the reference clock.
15 . A method, comprising:
storing a current value of a reference clock in a shift register based on a output clock generated by a PLL;
retrieving a plurality of shifted bits from the shift register;
comparing the plurality of shifted bits to a first bit in the shift register; and
determining whether there is a clock glitch based on the comparison.
16 . The method of claim 15 , wherein determining whether there is the clock glitch is performed using OR logic.
17 . The method of claim 15 , the plurality of shifted bits retrieved from the shift register are stored in a first set of latches, wherein the first set of latches are clocked using the output clock.
18 . The method of claim 17 , wherein the comparison is performed using a second set of latches, wherein outputs of the first set of latches serve as clock signals for the second set of latches.
19 . The method of claim 18 , further comprising:
inverting the first bit of the shift register at half of the second set of latches.
20 . The method of claim 17 , wherein a number of the plurality of shifted bits retrieved by the first set of latches from the shift register is equal to a multiple by which the PLL increases the frequency of the reference clock when generating the output clock.