Storage device, memory device, and computing system including the same
A memory device is provided. The memory device includes: a buffer memory; and a memory controller configured to: obtain map data and meta data for recovering the map data from at least one external storage device; store the map data and the meta data obtained from the at least one external storage device in the buffer memory, the buffer memory being allocated for the at least one external storage device; translate a logical address corresponding to the at least one external storage device into a physical address of the buffer memory; and send the map data and the meta data to the at least one external storage device in response to detecting a sudden power-off event.
1 . A memory device comprising:
an interface;
a buffer memory; and
a memory controller configured to:
obtain map data and meta data for recovering the map data from at least one external storage device;
store the map data and the meta data obtained from the at least one external storage device in the buffer memory, the buffer memory being allocated for the at least one external storage device;
translate a logical address corresponding to the at least one external storage device into a physical address of the buffer memory; and
send, using residual power of a power storage connected to the memory device, during a time period between detection of a sudden power-off event and the memory device being powered off, the map data and the meta data to the at least one external storage device in response to detecting the sudden power-off event,
wherein the memory device is configured to communicate with each of a host and the at least one external storage device via the interface.
2 . The memory device of claim 1 , wherein the at least one external storage device comprises a plurality of storage devices, and
wherein the memory controller is configured to obtain information for determining priorities of the plurality of storage devices from the plurality of storage devices, and determine the priorities based on the information.
3 . The memory device of claim 2 , wherein the information comprises any one or any combination of:
information about a residual power of a power storage connected with a bus connecting the host, the plurality of storage devices, and the memory device to each other;
information about a residual power of power storages respectively connected with the plurality of storage devices;
information about a residual storage space of each of the plurality of storage devices; and
information about an input/output bandwidth of each of the plurality of storage devices,
wherein the memory controller is configured to identify the information about the residual power of the power storage connected with the bus, and
wherein the memory controller is configured to, based on the residual power of the power storage connected with the bus being greater than or equal to a first reference value, store the map data and the meta data in the plurality of storage devices according to the priorities by using a first transfer scheme.
4 . The memory device of claim 1 , wherein the at least one external storage device comprises a plurality of storage devices,
wherein the memory controller is configured to identify information about the residual power of the power storage connected with the memory device, and
wherein the memory controller is configured to, based on the residual power of the power storage being greater than or equal to a first reference value, store the map data and the meta data in the plurality of storage devices according to priorities by using a first transfer scheme.
5 . The memory device of claim 4 , wherein the memory controller is configured to, based on the residual power of the power storage respectively connected with the plurality of storage devices being greater than or equal to a second reference value, store the map data and the meta data in the plurality of storage devices according to the priorities by using the first transfer scheme.
6 . The memory device of claim 4 , wherein the memory controller is configured to, based on the residual power of the power storage respectively connected with the plurality of storage devices being smaller than a second reference value:
select a storage device having a residual storage space for storing the map data and the meta data from among the plurality of storage devices; and
store the map data and the meta data in the selected storage device by using a second transfer scheme different from the first transfer scheme.
7 . The memory device of claim 4 , wherein the memory controller is configured to, based on the residual power of the power storage respectively connected with the plurality of storage devices being smaller than a second reference value:
divide the map data and the meta data into a plurality of data pieces; and
store the plurality of data pieces in the plurality of storage devices by using a second transfer scheme different from the first transfer scheme.
8 . The memory device of claim 4 , wherein the memory controller is configured to, based on the residual power of the power storage being smaller than the first reference value, store the map data and the meta data in a storage device having a highest priority of the priorities from among the plurality of storage devices by using a second transfer scheme different from the first transfer scheme.
9 . The memory device of claim 1 , wherein the interface comprises a compute express link (CXL) interface, and
wherein the memory device is configured to obtain the map data and the meta data from the at least one external storage device via the CXL interface, and send the map data and the meta data to the at least one external storage device via the CXL interface.
10 . The memory device of claim 1 , wherein the memory device is configured to communicate with a storage device which does not comprise a dynamic random access memory (DRAM) buffer.
11 . A storage device comprising:
an interface;
a nonvolatile memory device configured to store user data; and
a storage controller configured to:
generate map data corresponding to the nonvolatile memory device, which indicates a mapping relationship between a logical block address and a physical block address, and meta data for recovering the map data;
send the map data and the meta data to an external memory device comprising a buffer memory allocated for the storage device;
receive, during a time period between detection of a sudden power-off event and the storage device being powered off, the map data and the meta data output from the external memory device in response to the sudden power-off event; and
store the received map data and the received meta data in the nonvolatile memory device using residual power of a power storage connected to the storage device,
wherein the storage device is configured to communicate with each of a host and the external memory device using the interface.
12 . The storage device of claim 11 , wherein the storage controller is configured to send, to the external memory device, any one or any combination of information about the power storage connected with the storage device, information about a residual storage space of the nonvolatile memory device, and information about an input/output bandwidth of the storage device.
13 . The storage device of claim 11 , wherein the storage controller is configured to, in a sudden power-off recovery operation, read the map data stored in the nonvolatile memory device in response to a request from the external memory device and send the map data to the external memory device.
14 . The storage device of claim 11 , wherein the interface comprises a compute express link (CXL) interface, and
wherein the storage device is configured to obtain the map data and the meta data from the external memory device via the CXL interface, and send the map data and the meta data to the external memory device via the CXL interface.
15 . The storage device of claim 11 , wherein the storage device does not comprise a dynamic random access memory (DRAM) buffer.
16 . A computing system comprising:
a plurality of storage devices, each of which comprises a nonvolatile memory device and a storage controller configured to generate map data of the nonvolatile memory device and meta data for recovering the map data, the map data indicating a mapping relationship between a logical block address and a physical block address; and
a memory device comprising an interface, a memory controller configured to obtain the map data and the meta data from the plurality of storage devices, and a buffer memory configured to store the map data and the meta data, the buffer memory being allocated for the plurality of storage devices; and
wherein the memory device is configured to communicate with each of a host and the plurality of storage devices via the interface, and
wherein the memory controller is configured to send, using residual power of a power storage connected to the memory device, during a time period between detection of a sudden power-off event and the memory device being powered off, the map data and the meta data to the plurality of storage devices in response to detecting the sudden power-off event.
17 . The computing system of claim 16 , wherein the memory controller is configured to obtain, from the plurality of storage devices, any one or any combination of:
information about a residual power of at least one power storage connected with each of the plurality of storage devices;
information about a residual storage space of the nonvolatile memory device of each of the plurality of storage devices; and
information about an input/output bandwidth of each of the plurality of storage devices.
18 . The computing system of claim 17 , wherein the memory controller is configured to determine priorities for storing the map data and the meta data present in the buffer memory in the plurality of storage devices, based on the information obtained from the plurality of storage devices.
19 . The computing system of claim 18 , wherein the memory controller is configured to send the map data and the meta data to the plurality of storage devices according to the priorities in response to detecting the sudden power-off event.
20 . The computing system of claim 16 , wherein each of the plurality of storage devices does not comprise a dynamic random access memory (DRAM) buffer.