Data compression using instruction set architecture
In one embodiment, a computing system may set data to a first group of registers. The first group of registers may be configured to be accessed during a single operation cycle. The system may set a number of patterns to a second group of registers. Each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. The system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. The system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.
1 . A processor comprising:
an instruction set architecture configured to compress uncompressed input data, wherein the instruction set architecture comprises:
a compression module configured to autonomously and without involvement of software instructions:
read the uncompressed input data from a memory bank;
remove zero data elements from the uncompressed input data; and
write compressed output data to the memory bank;
a counter register configured to count a number of non-zero data elements in the uncompressed input data; and
one or more instructions configured to execute directly in hardware on the processor in machine code defined for the instruction set architecture, wherein the one or more instructions comprise a first instruction configured to set the compression module to (1) receive the uncompressed input data and (2) remove the zero data elements from the uncompressed input data.
2 . The processor of claim 1 , wherein the compression module is further configured to generate a bit mask comprising an array of flag elements, and wherein each flag element of the bit mask indicates a non-zero data element or a zero data element in the uncompressed input data.
3 . The processor of claim 2 , wherein the array of flag elements has an array length corresponding to a byte-length of the uncompressed input data.
4 . The processor of claim 1 , wherein the compression module is further configured to generate zero removed data, and wherein the instruction set architecture further comprises a shift register configured to receive the zero removed data from the compression module.
5 . The processor of claim 4 , wherein the shift register is configured to combine at least a portion of the zero removed data with one or more portions of previous zero removed data into output compressed data in a pre-determined byte length corresponding to an output bandwidth of the instruction set architecture.
6 . The processor of claim 5 , wherein the one or more portions of the previous zero removed data is loaded from a buffer to the shift register, and wherein the shift register is configured to write a remaining portion of the zero removed data back into the buffer.
7 . The processor of claim 1 , wherein the counter register is configured to hold a counter value that increments upon identifying a non-zero data element from the uncompressed input data.
8 . The processor of claim 1 , wherein the uncompressed input data is a portion of a continuous input data stream, and wherein the uncompressed input data has a byte length corresponding to a bandwidth limit of an input data interface of the compression module.
9 . A processor comprising:
an instruction set architecture configured to decompress compressed input data, wherein the instruction set architecture comprises:
a decompression module configured to autonomously and without involvement of software instructions:
read the compressed input data and bit mask data from a memory bank;
insert zero data elements into the compressed input data according to the bit mask data; and
write uncompressed output data to the memory bank;
a counter register configured to count a number of data elements in decompressed output data; and
one or more instructions configured to execute directly in hardware on the processor in machine code defined for the instruction set architecture, wherein the one or more instructions comprise a first instruction configured to set the decompression module to (1) receive the compressed input data and the bit mask data and (2) insert the zero data elements into the compressed input data according to the bit mask data.
10 . The processor of claim 9 , wherein the bit mask comprises an array of flag elements, and wherein each flag element of the bit mask data indicates a non-zero data element or a zero data element in decompressed output data.
11 . The processor of claim 10 , wherein the array of flag elements has an array length corresponding to a byte-length of the compressed input data.
12 . The processor of claim 9 , wherein the decompression module is further configured to generate zero inserted data, and wherein the instruction set architecture further comprises a first buffer and a second buffer.
13 . The processor of claim 12 , wherein the decompression module is further configured to output through a data output interface output uncompressed data, and wherein the output uncompressed data has a byte length corresponding to a bandwidth limit of the data output interface.
14 . The processor of claim 13 , wherein the decompression module is further configured to write a remaining portion of the zero inserted data into the first buffer in response to a determination that the remaining portion of the zero inserted data is within a size limit of the first buffer.
15 . The processor of claim 13 , wherein the decompression module is further configured to write a remaining portion of the zero inserted data into the first buffer and the second buffer in response to a determination that the remaining portion of the zero inserted data is beyond a size limit of the first buffer.
16 . The processor of claim 1 , wherein the instruction set architecture is configured to compress the uncompressed input data autonomously during a compression process without involvement of software instructions.
17 . The processor of claim 9 , wherein the counter register is configured to hold a counter value that increments upon generating a data element in the uncompressed output data.
18 . The processor of claim 1 , wherein the compression module is configured to:
read the uncompressed input data, remove zero data elements, and write compressed output data until all data bytes of the uncompressed input data are processed.
19 . The processor of claim 1 , wherein the processor is disposed within an augmented or virtual reality device.