Electronic device and method with hardware acceleration
An electronic device and method are provided. The method includes, in response to a result of a performed determination, between a processing-in-memory (PIM) operation and a non-PIM operation, being that a target operation included in an instruction set is the PIM operation, loading information regarding a PIM operation type of the target operation to a PIM operation register of an accelerator of the electronic device based on a performed determination that input data, for use in the target operation, is arranged in a memory of the accelerator according to a characteristic of the target operation, and controlling, using a PIM operation execution instruction, one or more PIM processing elements (PEs) of the memory to perform the target operation using the arranged input data and the information regarding the operation type loaded in the PIM operation register.
1 . A processor-implemented method of operating an electronic device, the method comprising:
in response to a result of a performed determination, between a processing-in-memory (PIM) operation and a non-PIM operation, being that a target operation included in an instruction set is the PIM operation:
loading information regarding a PIM operation type of the target operation to a PIM operation register of an accelerator of the electronic device based on a performed determination that input data, for use in the target operation, is arranged in a memory of the accelerator according to a characteristic of the target operation; and
controlling, using a PIM operation execution instruction, one or more PIM processing elements (PEs) of the memory to perform the target operation using the arranged input data and the information regarding the operation type loaded in the PIM operation register,
wherein the controlling further comprises storing a status of the PIM operation in the PIM operation register.
2 . The method of claim 1 , wherein the controlling comprises controlling the PIM operation to be performed in a portion of a plurality of memory banks included in the memory based on a bit field of the PIM operation execution instruction.
3 . The method of claim 1 , wherein the controlling comprises controlling the one or more PIM PEs in at least a portion of the memory to perform the PIM operation and restricting access to the at least portion of the memory by an arbitrary instruction, also included in the instruction set, while the one or more PIM PEs are performing the PIM operation.
4 . The method of claim 1 , further comprising, in response to a determination that the input data is firstly arranged not according to the characteristics of the target operation, rearranging the input data according to the characteristic of the PIM operation using a load/store instruction to access the memory.
5 . The method of claim 1 , wherein the instruction set comprises the PIM operation execution instruction.
6 . The method of claim 1 , further comprising rearranging, according to a predetermined arrangement compatible with one or more other components of the accelerator, a result of the PIM operation using a load/store instruction to access the memory.
7 . A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform the method of claim 1 .
8 . The method of claim 1 ,
wherein the status of the PIM operation comprises status information that the PIM operation is being performed when the PIM operation is being performed, and status information that the PIM operation has terminated when the PIM operation has terminated, and
wherein the status information that the PIM operation has been terminated comprises status information regarding whether the PIM operation was successful.
9 . The method of claim 8 , further comprising identifying the status of the PIM operation stored in the PIM operation register, and determining, based on the identified status of the PIM operation, whether a result obtained through the PIM operation is to be excluded or whether a post-processing is necessary for the result obtained through the PIM operation.
10 . An electronic device comprising:
an accelerator including:
a memory including processing-in-memory (PIM) processing elements (PEs) respectively configured to perform a PIM operation;
a PIM operation register; and
one or more processors, separate from the memory, configured to:
in response to a result of a performed determination, between the PIM operation and a non-PIM operation, being that a target operation included in an instruction set is the PIM operation:
load information regarding a PIM operation type of the target operation to the PIM operation register based on a performed determination that input data, for use in the target operation, is arranged in the memory according to a characteristic of the target operation; and
control, using a PIM operation execution instruction, one or more of the PIM PEs to perform the target operation using the arranged input data and the information regarding the operation type loaded in the PIM operation register,
wherein the one or more processors are further configured to control a storing of a status of the PIM operation in the PIM operation register.
11 . The electronic device of claim 10 , wherein the PIM operation type is a multiplication operation type, and wherein the characteristic is information that indicates whether the one or more of the PIM PEs is to perform the target operation in parallel or serially.
12 . The electronic device of claim 10 , further comprising a host processor configured to control the electronic device and control the accelerator using the instruction set.
13 . The electronic device of claim 12 , wherein the one or more processors are configured to control the PIM operation to be performed in a portion of a plurality of memory banks included in the memory based on a bit field of the PIM operation execution instruction.
14 . The electronic device of claim 12 , wherein the one or more processors are configured to control the one or more PIM PEs in at least a portion of the memory to perform the PIM operation and restrict access to the at least portion of the memory by an arbitrary instruction, also included in the instruction set, while the one or more PIM PEs are performing the PIM operation.
15 . The electronic device of claim 12 , wherein the one or more processors are further configured to, in response to a determination that the input data is firstly arranged not according to the characteristics of the target operation, rearrange the input data according to the characteristic of the PIM operation using a load/store instruction to access the memory.
16 . The electronic device of claim 12 , wherein the instruction set comprises the PIM operation execution instruction.
17 . The electronic device of claim 12 , wherein the one or more processors are further configured to rearrange, according to a predetermined arrangement compatible with one or more other components of the accelerator, a result of the PIM operation using a load/store instruction to access the memory.
18 . The electronic device of claim 12 ,
wherein the status of the PIM operation comprises status information that the PIM operation is being performed when the PIM operation is being performed, and status information that the PIM operation has terminated when the PIM operation has terminated, and
wherein the status information that the PIM operation has been terminated comprises status information regarding whether the PIM operation was successful.
19 . The electronic device of claim 18 , wherein the one or more processors are further configured to identify the status of the PIM operation stored in the PIM operation register, and determine, based on the identified status of the PIM operation, whether a result obtained through the PIM operation is to be excluded or whether a post-processing is necessary for the result obtained through the PIM operation.
20 . An electronic device, comprising:
an accelerator comprising:
a memory including processing-in-memory (PIM) processing elements (PEs) respectively configured to perform a PIM operation;
a PIM operation register; and
one or more processors, separate from the memory, configured to:
in response to a result of a performed determination, between the PIM operation and a non-PIM operation, being that a target operation included in an instruction set is the PIM operation:
obtain information regarding a PIM operation type of the target operation based on a performed determination that input data, for use in the target operation, is arranged according to a characteristic of the target operation; and
control, using a PIM operation execution instruction, one or more of the PIM PEs to perform the target operation using the arranged input data and the obtained information regarding the operation type,
wherein the one or more processors are further configured to control a storing of a status of the PIM operation in the PIM operation register.