Systems and methods for adaptively detecting and mitigating RowHammer attacks against computer memories
Systems and methods for adaptively detecting and mitigating RowHammer attacks or events against computer memories have been described. In an illustrative, non-limiting embodiment, a system may include a memory controller, and a RowHammer detection circuit coupled to the memory controller, where the RowHammer detection circuit is configured to: receive a count of activate commands for a segment of a memory device, where the segment comprises one or more of a plurality of memory cell rows; and detect a RowHammer event based, at least in part, upon a determination that the count of activate commands meets at least one of a plurality of trigger levels. Either the RowHammer detection circuit, or a different circuit, can then apply at least one of a plurality of RowHammer mitigation techniques, wherein each of the plurality of RowHammer mitigation techniques corresponds to at least one of the plurality of trigger levels.
1 . A system, comprising:
a memory controller; and
a RowHammer detection circuit coupled to the memory controller, the RowHammer detection circuit configured to:
in response to execution of instructions of a target application, wherein the instructions cause activate commands to be sent to the memory device, receive a plurality of counts of activate commands, each count corresponding to a respective one of a plurality of initial segments of a memory device;
determine that a difference between a first count of activate commands directed to a first initial segment and a second count of activate commands directed to a second initial segment is outside of a selected range;
in response to the determination, modify a size of the first initial segment to define a first adjusted segment and modify a size of the second initial segment to define a second adjusted segment;
in response to a difference between a first adjusted count of activate commands corresponding to the first adjusted segment and a second adjusted count of activate commands corresponding to the second adjusted segment being within the selected range;
receive a count of activate commands for a segment of a memory device, wherein the segment comprises one or more of a plurality of memory cell rows; and
detect a RowHammer event in at least one of the first or second adjusted segments based, at least in part, upon a determination that the count of activate commands meets at least one of a plurality of trigger levels.
2 . The system of claim 1 , wherein to receive the count of activate commands, the RowHammer detection circuit is configured to:
select at least one of a plurality of counters of activate commands, wherein the selected counter corresponds to an address of the segment; and
retrieve, from the counter, the count of the activate commands.
3 . The system of claim 1 , wherein the plurality of trigger levels comprises three or more trigger levels comprising at least one trigger level corresponding to a lower category of the activate command counts, at least one trigger level corresponding to a medium category of the activate command counts, and at least one trigger level corresponding to a final category of a most allowed count of the activate commands.
4 . The system of claim 1 , wherein the RowHammer detection circuit is configured to select at least one of a plurality of mitigation actions, and wherein each of the mitigation actions corresponds to a different trigger level.
5 . A device comprising one or more electronic circuits, the device configured to:
execute instructions of a target application, wherein the instructions cause activate commands to be sent to a dynamic random-access memory (DRAM), wherein the DRAM comprises a plurality of memory cell rows;
determine a plurality of counts of the activate commands directed to a respective plurality of segments of the DRAM, wherein each segment comprises one or more of the plurality of memory cell rows;
determine that a first count of the activate commands directed to a first segment, and a second count of the activate commands directed to a second segment, are not within a desired leveling range;
adjust the size of the first and second segments to define an adjusted first segment and an adjusted second segment of a plurality of adjusted segments;
determine that an adjusted first count of the activate commands corresponding to the adjusted first segment is within a desired leveling range of an adjusted second count of the activate commands corresponding to the adjusted second segment; and
provide memory address ranges corresponding to the plurality of adjusted segments to a memory controller.
6 . The device of claim 5 , wherein the one or more electronic circuits are further configured to determine, based at least in part on the adjusted first count of the activate commands, a plurality of trigger levels for a plurality of counters of activate commands.
7 . The device of claim 6 , wherein the one or more electronic circuits are further configured to:
determine, during a second execution of a same or different target application that causes the activate commands to be sent to one or more same or different DRAM devices, a third count of the activate commands corresponding to the adjusted first portion of the memory rows; and
detect a RowHammer event based, at least in part, upon a determination that the third count has reached a particular trigger level among the plurality of trigger levels.
8 . A system, comprising:
a dynamic random-access memory (DRAM) having a plurality of segments, each segment defined by an address range of the DRAM; and
a memory controller coupled to the DRAM, the memory controller having a RowHammer detection circuit comprising:
a plurality of counters, each counter configured to count activate commands to a corresponding segment of the plurality of segments;
a plurality of trigger level registers configured to store a plurality of trigger levels, the plurality of trigger levels corresponding to increasing count values, in which each trigger level corresponds to a different mitigation technique;
wherein the RowHammer detection circuit is configured to, in response to instructions of a target application being executed, wherein the instructions cause activation commands to be sent to the DRAM, profile the DRAM by:
determining a plurality of counts of the activate commands directed to a respective plurality of initial segments of the DRAM, wherein each initial segment comprises a same number of memory cell rows;
determine that a first count of the activate commands directed to a first initial segment, and a second count of the activate commands directed to a second initial segment, are not within a desired leveling range;
adjust the size of the first and second initial segments to define an adjusted first segment and an adjusted second segment of a plurality of adjusted segments;
determine that an adjusted first count of the activate commands corresponding to the adjusted first segment is within a desired leveling range of an adjusted second count of the activate commands corresponding to the adjusted second segment; and
provide memory address ranges corresponding to the plurality of adjusted segments as the assigned address ranges for each counter of the plurality of counters;
wherein the RowHammer detection circuit is further configured to, after profiling the DRAM:
determine that a count value of any first one of the plurality of counters has reached a first trigger level of the plurality of trigger levels, and
in response to the first trigger level being reached, applying a mitigation technique to the DRAM corresponding to the first trigger level.
9 . The system of claim 8 , wherein the RowHammer detection circuit further comprises an assigned address range defining the corresponding segment for each counter of the plurality of counters.
10 . The system of claim 8 , wherein the RowHammer detection circuitry is configured to:
after the mitigation technique corresponding to the first trigger level is applied, determining that a count value of any second one of the plurality of counters has reached a second trigger level of the plurality of trigger levels, the second trigger level corresponding to a higher count value than the first trigger level; and
in response to the second trigger level being reached, applying a mitigation technique to the DRAM corresponding to the second trigger level.
11 . The system of claim 10 , wherein the RowHammer detection circuitry is configured to:
after the mitigation technique corresponding to the second trigger level is applied, determining that a count value of any third one of the plurality of counters has reached a third trigger level of the plurality of trigger levels, the third trigger level corresponding to a highest count value of the increasing count values; and
in response to the third trigger level being reached, applying a mitigation technique to the DRAM corresponding to the third trigger level, wherein the third trigger level stops a subsequent activate command from reaching the DRAM.
12 . The system of claim 11 , wherein the RowHammer detection circuit is configured to, in response to the third trigger level being reached, stopping the subsequent activate command from reaching the DRAM at least until a refresh time period ends.
13 . The system of claim 10 , wherein the RowHammer detection circuit is configured to apply the mitigation technique corresponding to the first trigger level by adjusting one or more timing parameters.
14 . The system of claim 13 , wherein the one or more timing parameters comprise at least one of: a minimum time between an activate and a subsequent precharge command, or a minimum time to re-activate a closed wordline.
15 . The system of claim 13 , wherein the RowHammer detection circuit is configured to apply the mitigation technique corresponding to the second trigger level by adjusting a frequency of refreshes.