Granted Patent B2

US 12,554,991 · App. 16/174,108 · Granted Feb 17, 2026

Inventors: Zhen Li (Beijing, CN); Qi Guo (Beijing, CN); Yunji Chen (Beijing, CN); Tianshi Chen (Beijing, CN)

Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED

G06N3/08G06F17/16G06N3/04G06N3/047

Abstract

Claims (70)

1 . An apparatus for neural network operations, the apparatus comprising:

a master computation circuit configured to transmit an input vector via an interconnection circuit; and

one or more slave computation circuits connected to the master computation circuit via the interconnection circuit,

wherein each of the one or more slave computation circuits is configured to:

respectively store a column weight vector of a weight matrix, and

multiply the input vector with the column weight vector to generate a first multiplication result, and

wherein the interconnection circuit is configured to:

combine one or more first multiplication results of the one or more slave computation circuits into a first multiplication vector, wherein each first multiplication result of the one or more first multiplication results is associated with a respective slave computation circuit of the one or more slave computation circuits, and

transmit the first multiplication vector to the master computation circuit,

wherein the master computation circuit is further configured to:

add a first bias vector to the first multiplication vector to generate a first biased vector,

activate the first biased vector by applying a first activation function to the first biased vector to generate a first activated vector,

sample the first activated vector by a Gibbs sampler to generate a first phase hidden layer vector, and

transmit the first phase hidden layer vector to the one or more slave computation circuits via the interconnection circuit,

wherein each of the one or more slave computation circuits is configured to:

multiply the column weight vector with an element of the first phase hidden layer vector to generate a second multiplication result vector, and

transmit the second multiplication result vector to the interconnection circuit, and

wherein the interconnection circuit is configured to:

add one or more second multiplication result vectors of the one or more slave computation circuits into a second multiplication vector, wherein each second multiplication result vector of the one or more second multiplication result vectors is associated with a respective slave computation circuit of the one or more slave computation circuits, and

transmit the second multiplication vector to the master computation circuit, wherein the master computation circuit is configured to:

add a second bias vector to the second multiplication vector to generate a second biased vector,

activate the second biased vector by applying a second activation function to the second biased vector to generate a second activated vector, and

sample the second activated vector by the Gibbs sampler to generate a second phase visible layer vector,

wherein the master computation circuit is configured to transmit the second phase visible layer vector to the one or more slave computation circuits via the interconnection circuit,

wherein each of the one or more slave computation circuits is configured to:

multiply the second phase visible layer vector with the column weight vector to generate a third multiplication result, and

transmit the third multiplication result to the interconnection circuit, and

wherein the interconnection circuit is configured to:

combine one or more third multiplication results of the one or more slave computation circuits into a third multiplication vector, wherein each third multiplication result of the one or more third multiplication results is associated with a respective slave computation circuit of the one or more slave computation circuits, and

transmit the third multiplication vector to the master computation circuit,

wherein the master computation circuit is configured to:

add a third bias vector to the third multiplication vector to generate a third biased vector, and

activate the third biased vector by applying a third activation function to the third biased vector to generate a third phase hidden layer vector,

wherein the master computation circuit is configured to transmit the input vector, the first phase hidden layer vector, the second phase visible layer vector, and the third phase hidden layer vector to the one or more slave computation circuits via the interconnection circuit,

wherein the one or more slave computation circuits are configured to:

calculate a first cross product between a transpose of the input vector and the first phase hidden layer vector,

calculate a second cross product between a transpose of the second phase visible layer vector and the third phase hidden layer vector, and

update the weight matrix based on a learning rate and a difference between the first cross product and the second cross product.

2 . The apparatus of claim 1 , wherein the one or more slave computation circuits are configured to update the first bias vector based on a learning rate and a difference between the first phase hidden layer vector and the third phase hidden layer vector.

3 . The apparatus of claim 1 , wherein the one or more slave computation circuits are configured to update the second bias vector based on a learning rate and a difference between the input vector and the second phase visible layer vector.

4 . A method for neural network operations, the method comprising:

transmitting, by a master computation circuit, an input vector via an interconnection circuit;

respectively storing, by each of one or more slave computation circuits connected to the master computation circuit via an interconnection circuit, a column weight vector of a weight matrix;

multiplying, by each of the one or more slave computation circuits, the input vector with the column weight vector to generate a first multiplication result;

combining, by the interconnection circuit, one or more first multiplication results of the one or more slave computation circuits into a first multiplication vector, wherein each first multiplication result of the one or more first multiplication results is associated with a respective slave computation circuit of the one or more slave computation circuits;

transmitting, by the interconnection circuit, the first multiplication vector to the master computation circuit,

adding, by the master computation circuit, a first bias vector to the first multiplication vector to generate a first biased vector,

activating, by the master computation circuit, the first biased vector by applying a first activation function to the first biased vector to generate a first activated vector, and

sampling, by the master computation circuit, the first activated vector by a Gibbs sampler to generate a first phase hidden layer vector,

transmitting, by the master computation circuit, the first phase hidden layer vector to the one or more slave computation circuits via the interconnection circuit;

multiplying, by each of the one or more slave computation circuits, the column weight vector with an element of the first phase hidden layer vector to generate a second multiplication result vector;

transmitting, by each of the one or more slave computation circuits, the second multiplication result vectors to the interconnection circuit;

adding, by the interconnection circuit, one or more second multiplication result vectors of the one or more slave computation circuits into a second multiplication vector, wherein each second multiplication result vector of the one or more second multiplication result vectors is associated with a respective slave computation circuit of the one or more slave computation circuits;

transmitting, by the interconnection circuit, the second multiplication vector to the master computation circuit,

adding, by the master computation circuit, a second bias vector to the second multiplication vector to generate a second biased vector,

activating, by the master computation circuit, the second biased vector by applying a second activation function to the second biased vector to generate a second activated vector, and

sampling, by the master computation circuit, the second activated vector by the Gibbs sampler to generate a second phase visible layer vector,

transmitting, by the master computation circuit, the second phase visible layer vector to the one or more slave computation circuits via the interconnection circuit;

multiplying, by each of the one or more slave computation circuits, the second phase visible layer vector with the column weight vector to generate a third multiplication result;

transmitting, by each of the one or more slave computation circuits, the third multiplication result to the interconnection circuit; and

combining, by the interconnection circuit, one or more third multiplication results of the one or more slave computation circuits into a third multiplication vector, wherein each third multiplication result of the one or more third multiplication results is associated with a respective slave computation circuit of the one or more slave computation circuits;

transmitting, by the interconnection circuit, the third multiplication vector to the master computation circuit,

adding, by the master computation circuit, a third bias vector to the third multiplication vector to generate a third biased vector,

activating, by the master computation circuit, the third biased vector by applying a third activation function to the third biased vector to generate a third phase hidden layer vector,

transmitting, by the master computation circuit, the input vector, the first phase hidden layer vector, the second phase visible layer vector, and the third phase hidden layer vector to the one or more slave computation circuits via the interconnection circuit,

calculating, by the one or more slave computation circuits, a first cross product between a transpose of the input vector and the first phase hidden layer vector,

calculating, by the one or more slave computation circuits, a second cross product between a transpose of the second phase visible layer vector and the third phase hidden layer vector, and

updating, by the one or more slave computation circuits, the weight matrix based on a learning rate and a difference between the first cross product and the second cross product.

5 . The method of claim 4 , further comprising updating, by the one or more slave computation circuits, the first bias vector based on a learning rate and a difference between the first phase hidden layer vector and the third phase hidden layer vector.

6 . The method of claim 4 , further comprising updating, by the one or more slave computation circuits, the second bias vector based on a learning rate and a difference between the input vector and the second phase visible layer vector.

Assignments (1)

Continuity (2)

References Cited (28)