IP Library › Granted Patent US 12,555,530
Granted Patent B2
US 12,555,530 · App. 18/748,424 · Granted Feb 17, 2026

Display device gradually decreasing initialization voltage when converting driving frequency to low frequency

Inventors: Sehyuk Park (Yongin-si, KR); Youngha Sohn (Yongin-si, KR); Jin-Wook Yang (Yongin-si, KR); Donggyu Lee (Yongin-si, KR); Sukhun Lee (Yongin-si, KR); Jae-Hyeon Jeon (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/3233G09G2300/0819G09G2300/0852G09G2300/0861G09G2310/08G09G2320/0247
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Quick Facts
Patent No.
US 12,555,530
App. No.
18/748,424
Granted
Feb 17, 2026
Kind
B2
Abstract

A display device includes: a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line, and switchable by a voltage of a first node; a second transistor connected to a data line and a second node, and switchable by a write scan signal; a capacitor connected to the first node and the second node; an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal, where the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency. When converting from the first frequency to the second frequency, in a k-th frame of the second frequency, a level of the initialization voltage may gradually decrease.

Claims (47)

1 . A display device comprising:

a light emitting element including an anode and a cathode;

a first transistor connected to the anode and a power line, and switchable by a voltage of a first node;

a second transistor connected to a data line and a second node, and switchable by a write scan signal;

a capacitor connected to the first node and the second node; and

an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal,

wherein the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency,

wherein when converting from the first frequency to the second frequency, from a start point to an end point of a k-th frame of the second frequency, a level of the initialization voltage gradually decreases, wherein k is a natural number.

2 . The display device of claim 1 , wherein in a k+1-th frame of the second frequency, the level of the initialization voltage gradually decreases.

3 . The display device of claim 2 , wherein an amount of decrease in the initialization voltage of the k-th frame is greater than an amount of decrease in the initialization voltage of the k+1-th frame.

4 . The display device of claim 3 , wherein a first voltage difference between a maximum value and a minimum value of the level of the initialization voltage in the k-th frame is greater than a second voltage difference between a maximum value and a minimum value of the level of the initialization voltage in the k+1-th frame.

5 . The display device of claim 3 , wherein the k-th frame and the k+1-th frame are adjacent to a point in time at which the first frequency is converted to the second frequency.

6 . The display device of claim 5 , wherein k is 1.

7 . The display device of claim 2 , wherein each of the k-th frame and the k+1-th frame comprises a plurality of cycle periods,

wherein the cycle periods comprise:

a write cycle period during which the write scan signal and the bias scan signal are applied; and

a plurality of holding cycle periods during which the write scan signal is not applied, and the bias scan signal is applied.

8 . The display device of claim 7 , wherein a level of the initialization voltage during the write cycle period of the k+1-th frame is the same as a level of the initialization voltage during the write cycle period of the k-th frame.

9 . The display device of claim 7 , wherein in each of the k-th frame and the k+1-th frame, a level of the initialization voltage during an h+1-th cycle period is lower than a level of the initialization voltage during an h-th cycle period, wherein h is a natural number.

10 . The display device of claim 7 , wherein a level of the initialization voltage during a p-th holding cycle period of the k+1-th frame is higher than a level of the initialization voltage during a p-th holding cycle period of the k-th frame, wherein p is a natural number.

11 . The display device of claim 7 , wherein in each of the k-th frame and the k+1-th frame, a level of the initialization voltage during an h+1-th cycle period is lower than or equal to a level of the initialization voltage during an h-th cycle period, wherein h is a natural number.

12 . The display device of claim 7 , wherein a level of the initialization voltage during a p-th holding cycle period of the k+1-th frame is higher than or equal to a level of the initialization voltage during a p-th holding cycle period of the k-th frame, wherein p is a natural number.

13 . The display device of claim 7 , further comprising a light emission control transistor connected to the first transistor and the anode, and switchable by a light emission signal, wherein each of the cycle periods is defined as one cycle of the light emission signal.

14 . The display device of claim 7 , wherein in the holding cycle periods of each of the k-th frame and the k+1-th frame, number of times the bias scan signal is applied per holding cycle period varies.

15 . The display device of claim 14 , wherein as an order of a holding cycle period among the holding cycle periods of each of the k-th frame and the k+1-th frame is later, the number of times the bias scan signal is applied per holding cycle period gradually increases.

16 . The display device of claim 7 , wherein in the holding cycle periods of each of the k-th frame and the k+1-th frame, a duration of an activation level of the bias scan signal varies.

17 . The display device of claim 16 , wherein as an order of a holding cycle period among the holding cycle periods of each of the k-th frame and the k+1-th frame is later, the duration of the activation level of the bias scan signal in the holding cycle period gradually increases.

18 . A display device comprising:

a light emitting element including an anode and a cathode;

a first transistor connected to the anode and a power line, and switchable by a voltage of a first node;

a second transistor connected to a data line and a second node, and switchable by a write scan signal;

a capacitor connected to the first node and the second node; and

an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal,

wherein the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency,

wherein when converting from the first frequency to the second frequency, in each of a k-th frame of the second frequency and a k+1-th frame of the second frequency, a level of the initialization voltage gradually changes, and an amount of change in the initialization voltage of the k-th frame is greater than an amount of change in the initialization voltage of the k+1-th frame, wherein k is a natural number,

wherein from a start point to an end point of the k-th frame of the second frequency, a level of the initialization voltage gradually decreases.

19 . The display device of claim 18 , wherein in the k+1-th frame, the level of the initialization voltage gradually decreases.

20 . The display device of claim 19 , wherein an amount of total decrease in the initialization voltage during the k-th frame is greater than an amount of total decrease in the initialization voltage during the k+1-th frame.

21 . An electronic device comprising a display device for providing images,

wherein the display device comprises:

a light emitting element including an anode and a cathode;

a first transistor connected to the anode and a power line, and switchable by a voltage of a first node;

a second transistor connected to a data line and a second node, and switchable by a write scan signal;

a capacitor connected to the first node and the second node; and

an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal,

wherein the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency,

wherein when converting from the first frequency to the second frequency, from a start point to an end point of a k-th frame of the second frequency, a level of the initialization voltage gradually decreases, wherein k is a natural number.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2024
From: PARK, SEHYUK; SOHN, YOUNGHA; YANG, JIN-WOOK; LEE, DONGGYU; LEE, SUKHUN; JEON, JAE-HYEON
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 068162/0050 →
Priority Claims (1)
KR 10-2023-0165633 · Nov 24, 2023 · national
Continuity (1)
Related Publication 20250174190A1 · May 29, 2025
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