Gate driver and display device including the same
A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.
1 . A gate driver comprising:
a first shift register connected to gate lines and sensing control lines, and configured to supply gate signals to the gate lines and sensing signals to the sensing control lines;
a second shift register connected to the gate lines and the sensing control lines, and configured to supply the gate signals to the gate lines and the sensing signals to the sensing control lines;
first switches connected between the first shift register and the gate lines, and between the first shift register and the sensing control lines; and
second switches connected between the second shift register and the gate lines, and between the second shift register and the sensing control lines,
wherein the gate lines are connected to first transistors, and the sensing control lines are connected to second transistors,
wherein the first switches are configured to be turned on via a single mode setting signal having a first logic level during display periods, and the second switches are configured to be turned on via the single mode setting signal having a second logic level during sensing periods between the display periods,
wherein the mode-setting signal is provided on a single signal line to both the first switches and the second switches, and the first and second switches do not simultaneously turned on,
wherein a reset signal is applied to every stage of the second shift register at a start of each sensing period to force all stages except a sensing-target stage to a gate-off level,
wherein each of the first shift register and the second shift register is disposed on a same side from the first switches and the second switches, and
wherein the first switches and the second switches are configured to selectively supply signals from one of the first shift register or the second shift register at a time.
2 . The gate driver according to claim 1 , wherein at least one of the first switches includes a first-sub switch and a second-sub switch, and at least one of the second switches includes a third-sub switch and a fourth-sub switch,
wherein the first-sub switch is connected between the first shift register and a gate line among the gate lines,
wherein the second-sub switch is connected between the first shift register and a sensing control line among the sensing control lines,
wherein the third-sub switch is connected between the second shift register and the gate line among the gate lines, and is connected to the first-sub switch, and
wherein the fourth-sub switch is connected between the second shift register and the sensing control line among the sensing control lines, and is connected to the second-sub switch.
3 . The gate driver according to claim 2 , wherein:
the first shift register comprises:
a first-sub shift register connected to the gate lines; and
a second-sub shift register connected to the sensing control lines; and
the second shift register comprises:
a third-sub shift register connected to the gate lines; and
a fourth-sub shift register connected to the sensing control lines,
wherein the first-sub switch is connected between the first-sub shift register and the gate line among the gate lines,
wherein the second-sub switch is connected between the second-sub shift register and the sensing control line among the sensing control lines,
wherein the third-sub switch is connected between the third-sub shift register and the gate line among the gate lines, and
wherein the fourth-sub switch is connected between the fourth-sub shift register and the sensing control line among the sensing control lines.
4 . The gate driver according to claim 3 , wherein the first-sub switch and the second-sub switch are turned on in response to the mode setting signal in display periods.
5 . The gate driver according to claim 4 , wherein the third-sub switch and the fourth-sub switch are turned on in response to the mode setting signal in a vertical blank period between the display periods.
6 . The gate driver according to claim 1 , wherein a start pulse is supplied to the second shift register at different times in sequential frames.
7 . The gate driver according to claim 1 , wherein the gate driver is one of an Amorphous Silicon TFT Gate driver circuit (ASG) or an Oxide Semiconductor TFT Gate driver circuit (OSG).
8 . The gate driver according to claim 1 , wherein the reset signal is a pulse synchronized with a vertical blanking interval, and is generated by a timing controller that is external to the second shift register.
9 . The gate driver according to claim 1 , wherein the second shift register is configured to receive a plurality of second start pulses within a single frame, such that a plurality of different sensing-target stages are sequentially activated during a single sensing period.
10 . The gate driver according to claim 1 , wherein the first shift register and the second shift register are each implemented as a plurality of cascaded stages, and each stage includes an output buffer that is reset by the reset signal.
11 . The gate driver according to claim 1 , wherein the first switches and the second switches each comprise thin film transistors formed of different semiconductor materials, such that the first switches are amorphous silicon TFTs and the second switches are oxide semiconductor TFTs.
12 . A display device comprising:
a display panel including gate lines, sensing control lines, and pixels connected to the gate lines and the sensing control lines;
a gate driver connected to the gate lines and the sensing control lines; and
a timing controller configured to supply a first start pulse and a second start pulse to the gate driver,
wherein the gate driver comprises:
a first shift register connected to the gate lines and the sensing control lines, and configured to supply gate signals to the gate lines and sensing signals to the sensing control lines in response to the first start pulse;
a second shift register connected to the gate lines and the sensing control lines, and configured to supply the gate signals to the gate lines and the sensing signals to the sensing control lines in response to the second start pulse;
first switches connected between the first shift register and the gate lines, and between the first shift register and the sensing control lines; and
second switches connected between the second shift register and the gate lines, and between the second shift register and the sensing control lines, and
wherein the gate lines are connected to first transistors, and the sensing control lines are connected to second transistors,
wherein the first switches are configured to be turned on via a single mode setting signal having a first logic level during display periods, and the second switches are configured to be turned on via the single mode setting signal having a second logic level during sensing periods between the display periods,
wherein the mode-setting signal is provided on a single signal line to both the first switches and the second switches, and the first and second switches do not simultaneously turned on,
wherein a reset signal is applied to every stage of the second shift register at a start of each sensing period to force all stages except a sensing-target stage to a gate-off level,
wherein the first shift register and the second shift register are disposed on a same side on the display panel,
wherein each of the first shift register and the second shift register is disposed on a same side from the first switches and the second switches, and
wherein the first switches and the second switches are configured to selectively supply signals from one of the first shift register or the second shift register at a time.
13 . The display device according to claim 12 , wherein the timing controller is configured to output the second start pulse at different times in sequential frames.
14 . The display device according to claim 12 , wherein the first switches are configured to be turned on during display periods, and the second switches are configured to be turned on during sensing periods between the display periods.
15 . The display device according to claim 12 , wherein at least one of the pixels comprises:
an organic light emitting diode;
a drive transistor including a gate electrode connected to a first node, a first electrode connected to an input terminal of a first power supply voltage, and a second electrode connected to a second node;
a first transistor among the first transistors, connected between a data line and the gate electrode of the drive transistor, and including a gate electrode connected to a gate line among the gate lines;
a second transistor among the second transistors, connected between a sensing line and the second node, and including a gate electrode connected to a sensing control line among the sensing control lines; and
a storage capacitor connected between the first node and the second node.
16 . A method of driving a display device having a plurality of rows of pixels connected to gate lines and sensing control lines, and to a gate driver, the method comprising:
sequentially applying gate signals to the gate lines from the gate driver during display periods; and
selecting a first row of pixels to sense pixel characteristics thereof after the display periods,
wherein the gate driver comprises:
a first shift register connected to the gate lines and the sensing control lines;
a second shift register connected to the gate lines and the sensing control lines;
first switches connected between the first shift register and the gate lines, and between the first shift register and the sensing control lines; and
second switches connected between the second shift register and the gate lines, and between the second shift register and the sensing control lines, and
wherein the gate lines are connected to first transistors, and the sensing control lines are connected to second transistors,
wherein the first switches are configured to be turned on via a single mode setting signal having a first logic level during display periods, and the second switches are configured to be turned on via the mode setting signal having a second logic level during sensing periods between the display periods,
wherein the mode-setting signal is provided on a single signal line to both the first switches and the second switches, and the first and second switches do not simultaneously turned on,
wherein a reset signal is applied to every stage of the second shift register at a start of each sensing period to force all stages except a sensing-target stage to a gate-off level,
wherein the first shift register and the second shift register are disposed on a same side on the display panel,
wherein each of the first shift register and the second shift register is disposed on a same side from the first switches and the second switches, and
wherein the first switches and the second switches are configured to selectively supply signals from one of the first shift register or the second shift register at a time.
17 . The method according to claim 16 , wherein the first switches are configured to be turned on during the display periods, and the second switches are configured to be turned on during a sensing period between the display periods.
18 . The method according to claim 16 , wherein:
the step of sequentially applying the gate signals to the gate lines comprises applying the gate signals in response to a first signal; and
the step of selecting the first row of pixels comprises selecting the first row based upon a second signal generated independently of the first signal.