Method and system for a programmable and generic processing-in-SRAM accelerator
View Patent ↗A system for in-memory computing comprises a volatile memory comprising at least a first layered subarray, wherein each subarray comprises a plurality of memory cells, and a plurality of sub-sense amplifiers connected to a read bitline of the first subarray of the memory, configured to compare a measured voltage of the read bitline to at least one threshold and provide at least one binary output corresponding to a logic operation based on whether the voltage of the read bitline is above or below the threshold. A method for in-memory computing is also disclosed.
1 . A system for in-memory computing, comprising:
a volatile memory comprising at least a first layered subarray, wherein each subarray comprises a plurality of memory cells; and
a plurality of sub-sense amplifiers connected to a read bitline of the first subarray of the memory, configured to compare a measured voltage of the read bitline to a threshold corresponding to the distinct logic operation and provide a binary output corresponding to the distinct logic operation based on whether the voltage of the read bitline is above or below the threshold.
2 . The system of claim 1 , wherein the logic operation is selected from NOR, XOR, and NAND.
3 . The system of claim 1 , wherein the plurality of sub-sense amplifiers comprises three sub-sense amplifiers; and
wherein the at least one threshold comprises at least three thresholds, corresponding to NOR, XOR, and NAND logic operations.
4 . The system of claim 1 , further comprising a multiplexer connected to the binary outputs of the plurality of sub-sense amplifiers, configured to select one of the binary outputs in response to a control signal.
5 . The system of claim 1 , wherein the memory is a random-access memory.
6 . The system of claim 5 , wherein the random-access memory is an in-processing static random-access memory (SRAM).
7 . The system of claim 1 , wherein the plurality of memory cells are 8T SRAM cells.
8 . The system of claim 4 , wherein the multiplexer is selected from a 2:1 multiplexer, a 3:1 multiplexer, and a 4:1 multiplexer.
9 . A method of in-memory computing, comprising:
storing a set of data in a layered subarray of a volatile memory;
comparing, with a set of sub-sense amplifiers, an analog voltage of a read bitline of the volatile memory to a set of corresponding voltage references, each voltage reference corresponding to a digital logic operation;
providing a set of corresponding binary output values from the sub-sense amplifiers; and
selecting, with a multiplexer, one of the set of corresponding binary output values.
10 . The method of claim 9 , wherein the three memory rows are three operand vectors stored in a memory.
11 . The method of claim 9 , wherein the memory is a random-access memory.
12 . The method of claim 11 , wherein the random-access memory is an in-processing static random-access memory (SRAM).
13 . The method of claim 10 , wherein the method is performed in a single memory cycle.
14 . The method of claim 9 , wherein the set of corresponding binary output values are three-input logic operations.
15 . The method of claim 14 , wherein the three-input logic operations are selected from XOR3, AND3, NOR3, and OR3.
16 . The system of claim 1 , wherein the plurality of sub-sense amplifiers comprises three sub-sense amplifiers connected to the read bitline of the first subarray of the memory, each of the three sub-sense amplifiers dedicated to distinct logic operations and are configured to, during a single memory read cycle, compare the measured voltage of the read bitline to the threshold corresponding to the respective distinct logic operation and provide the binary output corresponding to the respective distinct logic operation based on whether the voltage of the read bitline is above or below the threshold.
17 . The system of claim 16 , wherein a first sub-sense amplifier is configured to compare the measured voltage to a first threshold, wherein a second sub-sense amplifier is configured to compare the measured voltage to a second threshold, and third sub-sense amplifier is configured to compare the measured voltage to a third threshold.
18 . The system of claim 16 , wherein a first sub-sense amplifier is configured to perform a NOR logic operation, a second sub-sense amplifier is configured to perform a XOR logic operation, and a third sub-sense amplifier is configured to perform a NAND logic operation.
19 . The system of claim 1 , wherein the plurality of sub-sense amplifiers are simultaneously connected to the read bit line and configured to derive contents of the plurality of memory cells based on a fall time of the read bit line.