IP Library › Granted Patent US 12,555,721
Granted Patent B2
US 12,555,721 · App. 18/735,609 · Granted Feb 17, 2026

Multilayer ceramic capacitor including raised portion

Inventors: Akira Ishizuka (Nagaokakyo, JP); Shinichi Kokawa (Nagaokakyo, JP); Yasuyuki Shimada (Nagaokakyo, JP)
Assignee: Murata Manufacturing Co., Ltd.
H01G4/232H01G4/012H01G4/248H01G4/30
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Quick Facts
Patent No.
US 12,555,721
App. No.
18/735,609
Granted
Feb 17, 2026
Kind
B2
Abstract

A multilayer ceramic capacitor includes end-surface external electrodes and side-surface external electrodes. The end-surface external electrodes are respectively provided at end surfaces of a multilayer body and are respectively connected to end-surface connecting internal electrodes. The side-surface external electrodes are respectively provided at the side surfaces of the multilayer body and respectively connected to side-surface connecting internal electrodes. The end-surface connecting internal electrodes each include end surface opposing portion opposing the side-surface connecting internal electrode adjacent in a lamination direction, and an end surface lead-out portion extending from the end surface opposing portion to one of the end-surface external electrodes. The side-surface connecting internal electrodes each include a side surface opposing portion opposing the end-surface connecting internal electrodes adjacent in the lamination direction, and a side surface lead-out portion extending from the side surface opposing portion to one of the side-surface external electrodes.

Claims (16)

1 . A multilayer ceramic capacitor comprising:

a multilayer body including:

two end surfaces opposing each other in a length direction intersecting a lamination direction;

two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction;

two main surfaces opposing each other in the lamination direction;

internal electrodes including end-surface connecting internal electrodes and side-surface connecting internal electrodes provided in the lamination direction; and

dielectrics alternately laminated with the internal electrodes in the lamination direction;

end-surface external electrodes which are respectively provided at the two end surfaces of the multilayer body; and

side-surface external electrodes which are respectively provided at the two side surfaces of the multilayer body; wherein

in a cross section passing through the width direction and the lamination direction at a middle portion in the length direction, the multilayer body has a smallest dimension in the lamination direction in a middle portion of the multilayer body in the width direction;

in the cross section passing through the width direction and the lamination direction at the middle portion in the length direction, one of the two main surfaces includes a raised portion which is raised from the middle portion in the width direction toward the respective side surfaces; and

in the cross section passing through the width direction and the lamination direction at the middle portion in the length direction, the raised portion, the side surface, and the middle portion of the multilayer body in the width direction satisfy the following dimensional relationship in the lamination direction:

the middle portion of the multilayer body in the width direction<the side surface<the raised portion.

2 . The multilayer ceramic capacitor according to claim 1 , wherein, in the cross section passing through the width direction and the lamination direction at the middle portion in the length direction, the side-surface connecting internal electrodes are connected to each of the side-surface external electrodes.

3 . The multilayer ceramic capacitor according to claim 1 , wherein the side-surface external electrodes cover at least a portion of the raised portion.

4 . The multilayer ceramic capacitor according to claim 1 , wherein the side-surface external electrodes cover at least a portion of an apex of the raised portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2024
From: ISHIZUKA, AKIRA; KOKAWA, SHINICHI; SHIMADA, YASUYUKI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 067644/0709 →
Priority Claims (1)
JP 2020-185814 · Nov 6, 2020 · national
Continuity (2)
Continuation 17506925 · Oct 21, 2021
Related Publication 20240321519A1 · Sep 26, 2024
References Cited (7)
US 12040136B2 · Ishizuka · 2024 [cited by examiner]
US 20120320495A1 · Akazawa · 2012 [cited by examiner]
US 20150116897A1 · Sawada · 2015 [cited by examiner]
US 20160104575A1 · Nakazawa · 2016 [cited by examiner]
JP 2004111489A · 2004 [cited by examiner]
JP 2016157904A · 2016 [cited by examiner]
Ishizuka et al., “Multilayer Ceramic Capacitor With Reduced Equivalent Series Inductance”, U.S. Appl. No. 17/506,925, filed Oct. 21, 2021. [cited by applicant]