Semiconductor structure having a backside contact with backside sidewall spacers
A semiconductor structure includes a source/drain region having a backside surface disposed in a backside interlayer dielectric layer, a backside contact disposed in the backside interlayer dielectric layer, wherein the backside contact is disposed on the backside surface of the source/drain region, backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the source drain region, and a backside power rail connected to the source/drain region through the backside contact.
1 . A semiconductor structure, comprising:
a source/drain region having a backside surface disposed in a backside interlayer dielectric layer;
a backside contact disposed in the backside interlayer dielectric layer, wherein the backside contact is disposed on the backside surface of the source/drain region;
backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the source drain region; and
a backside power rail connected to the source/drain region through the backside contact;
wherein the backside sidewall spacers comprise multiple segments of a first sidewall spacer and a second sidewall spacer in an alternating pattern.
2 . The semiconductor structure of claim 1 , further comprising a first field-effect transistor disposed on the backside interlayer dielectric layer and a second field-effect transistor disposed on the backside interlayer dielectric layer and adjacent the first field-effect transistor.
3 . The semiconductor structure of claim 2 , wherein the first field-effect transistor comprises a first gate structure, and the second field-effect transistor comprises a second gate structure.
4 . The semiconductor structure of claim 3 , where the backside interlayer dielectric layer is in contact with the first gate structure and the second gate structure.
5 . The semiconductor structure of claim 3 , where a portion of the source/drain region extends above the backside interlayer dielectric layer and is located between the first field-effect transistor and the second field-effect transistor.
6 . The semiconductor structure of claim 5 , wherein the first field-effect transistor and the second field-effect transistor comprise respective nanosheet field-effect transistor devices.
7 . The semiconductor structure of claim 1 , further comprising a first nanosheet field-effect transistor disposed on the backside interlayer dielectric layer and a second nanosheet field-effect transistor disposed on the backside interlayer dielectric layer and adjacent the first nanosheet field-effect transistor;
wherein the first nanosheet field-effect transistor and the second nanosheet field-effect transistor comprise inner spacers that are composed of a segment of one of the first sidewall spacer and the second sidewall spacer.
8 . A semiconductor structure, comprising:
a first source/drain region having a backside surface disposed in a backside interlayer dielectric layer;
a second source/drain region disposed on the backside interlayer dielectric layer and located adjacent the first source/drain region;
a backside contact disposed in the backside interlayer dielectric layer and in contact with the backside surface of the first source/drain region; and
backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the first source/drain region;
wherein the backside sidewall spacers comprise multiple segments of a first sidewall spacer and a second sidewall spacer in an alternating pattern.
9 . The semiconductor structure of claim 8 , further comprising a backside power rail connected to the first source/drain region through the backside contact.
10 . The semiconductor structure of claim 8 , further comprising a first field-effect transistor disposed on the backside interlayer dielectric layer and a second field-effect transistor disposed on the backside interlayer dielectric layer and adjacent the first field-effect transistor.
11 . The semiconductor structure of claim 10 , wherein the first field-effect transistor comprises a first gate structure, and the second field-effect transistor comprises a second gate structure.
12 . The semiconductor structure of claim 11 , where the backside interlayer dielectric layer is in contact with the first gate structure and the second gate structure.
13 . The semiconductor structure of claim 12 , where a portion of the first source/drain region extends above the backside interlayer dielectric layer and is located between the first field-effect transistor and the second field-effect transistor.
14 . The semiconductor structure of claim 13 , wherein the first field-effect transistor and the second field-effect transistor comprise respective nanosheet field-effect transistor devices.
15 . An integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a source/drain region having a backside surface disposed in a backside interlayer dielectric layer;
a backside contact disposed in the backside interlayer dielectric layer, wherein the backside contact is disposed on the backside surface of the source/drain region;
backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the source drain region; and
a backside power rail connected to the source/drain region through the backside contact;
wherein the backside sidewall spacers comprise multiple segments of a first sidewall spacer and a second sidewall spacer in an alternating pattern.
16 . The integrated circuit of claim 15 , wherein the at least one of the one or more semiconductor structures further comprises a first nanosheet field-effect transistor disposed on the backside interlayer dielectric layer and a second nanosheet field-effect transistor disposed on the backside interlayer dielectric layer and adjacent the first nanosheet field-effect transistor.
17 . The integrated circuit of claim 16 , wherein the first nanosheet field-effect transistor comprises a first gate structure, and the second nanosheet field-effect transistor comprises a second gate structure, and the backside interlayer dielectric layer is in contact with the first gate structure and the second gate structure.
18 . The integrated circuit of claim 17 , where a portion of the source/drain region extends above the backside interlayer dielectric layer and is located between the first field-effect transistor and the second field-effect transistor.
19 . The integrated circuit of claim 18 , wherein the first field-effect transistor and the second field-effect transistor comprise respective nanosheet field-effect transistor devices.
20 . The integrated circuit of claim 15 , wherein the at least one of the one or more semiconductor structures further comprises a first nanosheet field-effect transistor disposed on the backside interlayer dielectric layer and a second nanosheet field-effect transistor disposed on the backside interlayer dielectric layer and adjacent the first nanosheet field-effect transistor;
wherein the first nanosheet field-effect transistor and the second nanosheet field-effect transistor comprise inner spacers that are composed of a segment of one of the first sidewall spacer and the second sidewall spacer.