Display device
In order to achieve the above-described technical benefits, according to an aspect of the present disclosure, a display device includes a stretchable lower substrate which includes an active area and a non-active area disposed at the outside of the active area; a pattern layer which is disposed on the lower substrate and includes a plurality of plate patterns and a plurality of line patterns; a plurality of pixels which is disposed above each of the plurality of plate patterns in the active area; and a plurality of connection lines which is disposed above the plurality of line patterns to connect the plurality of pixels, and the plurality of connection lines includes a high potential voltage line and a low potential voltage line which overlap each other in each of the plurality of plate patterns.
1 . A display device, comprising:
a stretchable lower substrate which includes an active area and a non-active area disposed outside of the active area;
a pattern layer which is disposed on the lower substrate and includes a plurality of plate patterns and a plurality of line patterns;
a plurality of pixels which is disposed above the plurality of plate patterns in the active area; and
a plurality of connection lines which is disposed above the plurality of line patterns and connects the plurality of pixels to each other,
wherein the plurality of connection lines includes respective high potential voltage lines and respective low potential voltage lines which overlap each other on each of the plurality of plate patterns,
wherein:
the high potential voltage line includes:
a high potential voltage main line extending in a second direction, and
a high potential voltage sub line which is electrically connected to the high potential voltage main line and extends in a first direction transverse the second direction; and
the low potential voltage line includes:
a low potential voltage main line extending in the second direction, and
a low potential voltage sub line which is electrically connected to the low potential voltage main line and extends in the first direction.
2 . The display device according to claim 1 , wherein:
the plurality of plate patterns includes:
a plurality of 1a-th plate patterns, and
a plurality of 1b-th plate patterns which is alternately disposed with the plurality of 1a-th plate patterns in the first direction;
the high potential voltage main line is disposed on the plurality of 1a-th plate patterns; and
the low potential voltage main line is disposed on the plurality of 1b-th plate patterns.
3 . The display device according to claim 2 , wherein the high potential voltage sub line is electrically connected to the high potential voltage main line disposed on the plurality of 1a-th plate patterns and extends to the plurality of 1b-th plate patterns adjacent to the plurality of 1a-th plate patterns.
4 . The display device according to claim 3 , wherein the high potential voltage sub line includes:
a first high potential voltage sub line disposed below the high potential voltage main line on at least one of the plurality of 1a-th plate patterns;
a second high potential voltage sub line disposed on at least one of the plurality of line patterns; and
a third high potential voltage sub line disposed below the low potential voltage main line on at least one of the plurality of 1b-th plate patterns.
5 . The display device according to claim 4 , wherein the low potential voltage main line and the third high potential voltage sub line are disposed to overlap each other.
6 . The display device according to claim 4 , further comprising:
a transistor including a gate electrode, an active layer, a source electrode, and a drain electrode disposed on at least one of the plurality of plate patterns,
wherein the first high potential voltage sub line and the third high potential voltage sub line are formed of the same material as any one of the gate electrode, the source electrode, and the drain electrode of the transistor; and
wherein the second high potential voltage sub line is formed of the same material as the plurality of connection lines.
7 . The display device according to claim 2 , wherein the low potential voltage sub line is electrically connected to the low potential voltage main line disposed on the plurality of 1b-th plate patterns and extends to the plurality of 1a-th plate patterns adjacent to the plurality of 1b-th plate patterns.
8 . The display device according to claim 7 , wherein the low potential voltage sub line includes:
a first low potential voltage sub line disposed on at least one of the plurality of 1b-th plate patterns and one of the plurality of line patterns;
a second low potential voltage sub line disposed on at least one of the plurality of 1a-th plate patterns; and
a third low potential voltage sub line disposed below the high potential voltage main line on the at least one of the plurality of 1a-th plate patterns.
9 . The display device according to claim 8 , wherein the high potential voltage main line and the third low potential voltage sub line are disposed to overlap each other.
10 . The display device according to claim 8 , further comprising:
a transistor including a gate electrode, an active layer, a source electrode, and a drain electrode disposed on one of the plurality of plate patterns,
wherein the first low potential voltage sub line is formed of the same material as the plurality of connection lines; and
wherein the third low potential voltage sub line is formed of the same material as any one of the gate electrode, the source electrode, and the drain electrode of the transistor.
11 . The display device according to claim 1 , wherein connection lines extending in the second direction, among the plurality of connection lines, include at least one of the high potential voltage main line, the low potential voltage main line, and a plurality of data lines.
12 . The display device according to claim 1 , wherein a connection line extending in the first direction, among the plurality of connection lines, includes at least one of a scan line, an emission signal line, and an initialization voltage line.
13 . The display device according to claim 1 , wherein in the non-active area, a plurality of data drivers are disposed in a first direction and a plurality of gate drivers are disposed in a second direction transverse the first direction, and the number of data drivers is larger than the number of gate drivers.
14 . A display device, comprising:
a substrate;
a pattern layer on the substrate, the pattern layer including:
a first plate pattern,
a second plate pattern adjacent the first plate pattern, and
a line pattern that connects the first plate pattern to the second plate pattern;
a first pixel on the first plate pattern;
a second pixel on the second plate pattern;
a low potential voltage line that overlaps the second plate pattern; and
a high potential voltage line that overlaps the first plate pattern and the second plate pattern, the high potential voltage line overlapping the low potential voltage line over the second plate pattern,
wherein:
the high potential voltage line includes:
a high potential voltage main line that extends in a second direction, and
a high potential voltage sub line electrically connected to the high potential voltage main line and that extends in a first direction transverse the second direction; and
the low potential voltage line includes:
a low potential voltage main line that extends in the second direction, and
a low potential voltage sub line electrically connected to the low potential voltage main line and that extends in the first direction.
15 . The display device of claim 14 , wherein the high potential voltage sub line includes:
a first high potential voltage sub line disposed below the high potential voltage main line on the first plate pattern;
a second high potential voltage sub line disposed on the line pattern; and
a third high potential voltage sub line disposed below the low potential voltage main line on the second plate pattern.
16 . The display device of claim 15 , further comprising:
a third plate pattern adjacent the second plate pattern,
wherein the low potential voltage sub line includes:
a first low potential voltage sub line disposed on the second plate pattern and on a second line pattern that connects the second plate pattern to the third plate pattern;
a second low potential voltage sub line disposed on the third plate pattern; and
a third low potential voltage sub line disposed below a second high potential voltage main line on the third plate pattern.
17 . The display device of claim 16 , further comprising:
a transistor including a gate electrode, an active layer, a source electrode, and a drain electrode disposed on one of the plurality of plate patterns,
wherein the first high potential voltage sub line and the third high potential voltage sub line are formed of the same material as any one of the gate electrode, the source electrode, and the drain electrode of the transistor.
18 . The display device of claim 16 , further comprising:
a transistor including a gate electrode, an active layer, a source electrode, and a drain electrode disposed on the second plate pattern,
wherein the third low potential voltage sub line is formed of the same material as any one of the gate electrode, the source electrode, and the drain electrode of the transistor.