IP Library › Granted Patent US 12,560,957
Granted Patent B2
US 12,560,957 · App. 18/498,660 · Granted Feb 24, 2026

Linear regulator

Inventor: Daisuke Uchimoto (Kyoto, JP)
Assignee: Rohm Co., Ltd.
G05F1/575G05F1/573
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Quick Facts
Patent No.
US 12,560,957
App. No.
18/498,660
Granted
Feb 24, 2026
Kind
B2
Abstract

A linear regulator includes an input terminal configured to receive an input voltage, an output terminal configured to be applied with an output voltage, an output transistor connected between the input terminal and the output terminal, and constituted by a P-channel MOSFET, a gate control circuit configured to control a gate voltage of the output transistor to stabilize the output voltage at a target voltage based on a feedback voltage corresponding to the output voltage, and an additional circuit, wherein a control range of the gate voltage controlled by the gate control circuit is equal to or higher than a predetermined lower limit voltage, and wherein the additional circuit is configured to lower the gate voltage to below the lower limit voltage when the output voltage falls below a determination voltage lower than the target voltage.

Claims (17)

1 . A linear regulator, comprising:

an input terminal configured to receive an input voltage;

an output terminal configured to be applied with an output voltage;

an output transistor connected between the input terminal and the output terminal, and constituted by a P-channel MOSFET;

a gate control circuit configured to control a gate voltage of the output transistor to stabilize the output voltage at a target voltage based on a feedback voltage corresponding to the output voltage;

an additional circuit; and

an overcurrent protection circuit configured to detect that a value of an output current flowing through the output transistor exceeds a predetermined overcurrent determination value,

wherein a control range of the gate voltage controlled by the gate control circuit is equal to or higher than a predetermined lower limit voltage,

wherein the additional circuit is configured to lower the gate voltage to below the lower limit voltage when the output voltage falls below a determination voltage lower than the target voltage, and

wherein when the overcurrent protection circuit detects that the value of the output current exceeds the overcurrent determination value, the gate control circuit controls the gate voltage so as to limit the value of the output current to the overcurrent determination value or less, and the additional circuit stops an operation which causes a decrease in the gate voltage regardless of the output voltage.

2 . The linear regulator of claim 1 , wherein the gate control circuit controls the gate voltage based on a comparison result of the feedback voltage and a predetermined first reference voltage, and

wherein the additional circuit compares the feedback voltage with a predetermined second reference voltage lower than the first reference voltage and lowers the gate voltage to below the lower limit voltage when the feedback voltage is lower than the second reference voltage.

3 . The linear regulator of claim 2 , wherein the additional circuit includes an additional transistor provided between a gate of the output transistor and a ground, and an active circuit configured to control a state of the additional transistor based on the feedback voltage and the second reference voltage, and

wherein the active circuit controls the additional transistor to be in an off-state when the feedback voltage is higher than the second reference voltage, and lowers the gate voltage to below the lower limit voltage by generating a current flowing from the gate of the output transistor to the ground through the additional transistor when the feedback voltage is lower than the second reference voltage.

4 . The linear regulator of claim 3 , wherein the active circuit is a comparator or an amplifier, and is configured to control the state of the additional transistor by controlling a voltage of a control electrode of the additional transistor based on the feedback voltage and the second reference voltage.

5 . The linear regulator of claim 2 , further comprising:

a voltage generation circuit configured to generate the first reference voltage based on the input voltage and generate the second reference voltage based on the first reference voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2023
From: UCHIMOTO, DAISUKE
To: ROHM CO., LTD.
Reel/Frame 065425/0926 →
Priority Claims (1)
JP 2022-179450 · Nov 9, 2022 · national
Continuity (1)
Related Publication 20240152168A1 · May 9, 2024
References Cited (3)
US 20110121802A1 · Zhu · 2011 [cited by examiner]
US 20190302820A1 · Yasusaka · 2019 [cited by examiner]
WO WO2021054027 · 2021 [cited by applicant]