Device and method for adaptive bus protocol
Apparatuses and methods are disclosed. The apparatus includes a bus master including processing circuitry and a bus interface. The processing circuitry is configured to control operation of the bus master such that the bus master transmits a first address to a bus slave through a bus in a first mode and to transmit a second address having a same first length as the first address to the bus slave through the bus in a second mode. The bus interface is configured to generate the second address such that the second address includes a plurality of short addresses corresponding to a plurality of special function registers of the bus slave, respectively, in the second mode.
1 . An apparatus comprising:
a bus master including,
processing circuitry configured to,
dynamically set a mode to a first mode when accessing a single special function register, and to a second mode when accessing a plurality of special function registers, and
control operation of the bus master such that the bus master transmits a first address corresponding to the single special function register to a bus slave through a bus in the first mode and to transmit a second address having a same first length as the first address and corresponding to the plurality of special functions registers to the bus slave through the bus in the second mode; and
a bus interface configured to, in the second mode, generate the second address such that the second address includes a plurality of short addresses corresponding to the plurality of special function registers of the bus slave, respectively.
2 . The apparatus of claim 1 , wherein
the processing circuitry is configured to control operation of the bus master such that the bus master transmits or receives first data through the bus in the first mode and to transmit or receive second data through the bus in the second mode, and
the second data has a same second length as the first data and includes a plurality of first values corresponding to the plurality of special function registers, respectively.
3 . The apparatus of claim 1 , wherein
the bus interface includes a first base address register configured to store a base address, and
the bus interface is further configured to generate a plurality of address offsets as the plurality of short addresses based on the base address and a plurality of absolute addresses of the plurality of special function registers in the second mode.
4 . The apparatus of claim 3 , wherein
the bus master is further configured to transmit the base address to the bus slave through the bus.
5 . The apparatus of claim 4 , further comprising:
the bus; and
the bus slave,
wherein the bus slave includes the plurality of special function registers, a second base address register configured to store the base address and a register controller configured to identify the plurality of special function registers based on the base address and the plurality of short addresses in the second mode.
6 . The apparatus of claim 5 , wherein
the register controller is further configured to generate third data and to transmit the third data to the bus master through the bus in the second mode, and
the register controller is configured to generate the third data based on information received from the plurality of special function registers.
7 . The apparatus of claim 1 , wherein
the plurality of special function registers include a first special function register having a first absolute address and a second special function register having a second absolute address, and
the bus interface is further configured to generate the second address including a difference between the first absolute address and the second absolute address.
8 . The apparatus of claim 1 , wherein
the processing circuitry is further configured to control operation of the bus master such that the bus master transmits a mode signal indicating the first mode or the second mode to the bus slave through the bus.
9 . The apparatus of claim 8 , wherein
the mode signal is a sideband signal of the bus.
10 . A method comprising:
dynamically setting a mode to a first mode when accessing a single special function register, and to a second mode when accessing a plurality of special function registers;
transmitting a first address corresponding to the single special function register to a bus slave through a bus in the first mode;
generating a second address corresponding to the plurality of special functions registers in the second mode such that the second address includes a plurality of short addresses corresponding to the plurality of special function registers of the bus slave, respectively, and has a same first length as the first address; and
transmitting the second address to the bus slave through the bus in the second mode.
11 . The method of claim 10 , further comprising:
transmitting first data to the bus slave through the bus in the first mode;
generating second data in the second mode such that the second data includes a plurality of first values corresponding to the plurality of special function registers, respectively, and has a same second length as the first data; and
transmitting the second data to the bus slave through the bus in the second mode.
12 . The method of claim 10 , further comprising:
receiving first data from the bus slave through the bus in the first mode;
receiving second data from the bus slave through the bus in the second mode; and
extracting a plurality of second values corresponding to the plurality of special function registers, respectively, from the second data in the second mode.
13 . The method of claim 10 , further comprising:
determining a base address based on a plurality of absolute addresses of the plurality of special function registers in the second mode,
wherein the generating the second address includes generating a plurality of address offsets based on the base address and the plurality of absolute addresses.
14 . The method of claim 13 , further comprising:
transmitting the base address to the bus slave through the bus.
15 . An apparatus comprising:
a bus configured to receive a first address from a bus master in a first mode and a second address having a same first length as the first address from the bus master in a second mode,
wherein the bus includes
a plurality of slave interfaces configured to communicate with a plurality of bus slaves, respectively; and
a controller configured to control the plurality of slave interfaces to have access to a plurality of special function registers based on the second address in the second mode, each of the plurality of bus slaves including one of the plurality of special function registers.
16 . The apparatus of claim 15 , wherein
the bus is further configured to receive first data from the bus master in the first mode and to receive second data, which has a same second length as the first data, from the bus master in the second mode, and
the controller is further configured to extract a plurality of first values corresponding to the plurality of special function registers, respectively, from the second data and to provide the extracted values to the plurality of slave interfaces, respectively, in the second mode.
17 . The apparatus of claim 16 , wherein
the bus master is further configured to generate the second address based on the plurality of special function registers and the second data including the plurality of first values, and to transmit the second address and the second data to the bus in the second mode.
18 . The apparatus of claim 15 , wherein
the controller is further configured to generate third data including a plurality of second values, which are received from the plurality of slave interfaces, respectively, and to transmit the third data to the bus master in the second mode.
19 . The apparatus of claim 15 , wherein
the bus is further configured to receive a mode signal indicating the first mode or the second mode from the bus master through the bus.
20 . The apparatus of claim 19 , wherein
the mode signal is a sideband signal of the bus.