Pixel with gate of driving transistor directly connected to drain and display device including the same
A pixel according to one or more embodiments of the present disclosure may include a transistor including a gate terminal connected to a first node, a first terminal connected to a first power, and a second terminal connected to a second node having a same potential as the first node, a capacitor including a first capacitor terminal connected to a data power, and a second capacitor terminal connected to the first node, and a light emitting diode including a first diode terminal connected to the second node, and a second diode terminal connected to a second power.
1 . A pixel comprising:
a light emitting diode configured to output light based on a driving current, and comprising a first terminal, and a second terminal configured to receive a second power;
a transistor configured to generate the driving current, and comprising a first terminal configured to receive a first power, a second terminal electrically connected to the first terminal of the light emitting diode, and a gate terminal directly electrically connected to the first terminal of the transistor; and
a capacitor comprising a first terminal configured to receive a data power and a second terminal electrically connected to the gate terminal of the transistor.
2 . The pixel of claim 1 , wherein the gate terminal of the transistor and the second terminal of the capacitor are directly electrically connected to a first node.
3 . The pixel of claim 2 , wherein the first terminal of the light emitting diode and the second terminal of the transistor are directly electrically connected to a second node.
4 . The pixel of claim 3 , wherein the first node is directly electrically connected to the second node.
5 . The pixel of claim 3 , wherein no transistor is electrically connected between the first node and the second node.
6 . The pixel of claim 2 , wherein a frame period for the pixel comprises:
an initialization period during which the gate terminal is initialized;
a compensation period during which a threshold voltage of the transistor is compensated;
a data writing period during which the data power is applied to the first node; and
a light emitting period during which the light emitting diode emits light.
7 . The pixel of claim 6 , wherein the first power has a first voltage level, and a second voltage level that is greater than the first voltage level,
wherein the data power has a third voltage level, and a fourth voltage level that is greater than the third voltage level, and
wherein the second power has a fifth voltage level equal to the first voltage level, and a sixth voltage level that is equal to the second voltage level.
8 . The pixel of claim 7 , wherein, in the initialization period:
the first power has the first voltage level;
the data power has the third voltage level; and
the second power has the fifth voltage level.
9 . The pixel of claim 7 , wherein, in the compensation period:
the first power has the second voltage level;
the data power has the third voltage level; and
the second power has the sixth voltage level.
10 . The pixel of claim 7 , wherein, in the data writing period:
the first power has the first voltage level;
the data power has the fourth voltage level; and
the second power has the fifth voltage level.
11 . The pixel of claim 7 , wherein, in the light emitting period:
the first power has the second voltage level;
the data power has the fourth voltage level; and
the second power has the fifth voltage level.
12 . The pixel of claim 2 , wherein the transistor further comprises a back gate terminal configured to receive a back gate voltage.
13 . The pixel of claim 12 , wherein a frame period for the pixel comprises:
an initialization period during which the gate terminal is initialized;
a compensation period during which a threshold voltage of the transistor is compensated;
a data writing period during which the data power is applied to the first node; and
a light emitting period during which the light emitting diode emits light, and
wherein the back gate voltage having a negative polarity is applied to the back gate terminal in the compensation period.
14 . The pixel of claim 1 , wherein the first terminal of the capacitor is directly electrically connected to the data power.
15 . A display device comprising:
a light emitting diode above a substrate;
an active pattern above the substrate, and comprising a source region configured to receive a first power, a drain region electrically connected to the light emitting diode, and a channel region between the source region and the drain region;
a first electrode above the substrate, and electrically connected to the light emitting diode; and
a second electrode above the first electrode, and configured to receive a data power.
16 . The display device of claim 15 , wherein the first electrode and the light emitting diode are electrically connected through the drain region of the active pattern.
17 . The display device of claim 15 , further comprising a third electrode above the substrate, and configured to receive a back gate voltage.
18 . The display device of claim 17 , wherein the third electrode is located between the first electrode and the second electrode.
19 . The display device of claim 15 , wherein the first electrode is located between the active pattern and the second electrode.
20 . The display device of claim 15 , wherein the active pattern is located between the first electrode and the second electrode.