ReDriver circuit
One example discloses a driver circuit, comprising: a first transistor (Q TN ) coupled to a first differential input (IN) and a power supply input (VCC); a second transistor (Q TP ) coupled to a second differential input (IP) and the power supply input; a third transistor (Q BN ) coupled to a first differential output (ON); a fourth transistor (Q BP ) coupled to a second differential output (OP); a first resistance (R P1 ) coupling the first transistor (Q TN ) to the third transistor (Q BN ); a second resistance (R P2 ) coupling the second transistor (Q TP ) to the fourth transistor (Q BP ); and a controller coupled to the power supply input; wherein the controller is configured to detect a ramp-down of a power supply coupled to the power supply input and in response disable a set of circuit elements in the driver circuit.
1 . A driver circuit, comprising:
a first transistor (Q TN ) coupled to a first differential input (IN) and a power supply input (VCC);
a second transistor (Q TP ) coupled to a second differential input (IP) and the power supply input;
a third transistor (Q BN ) coupled to a first differential output (ON);
a fourth transistor (Q BP ) coupled to a second differential output (OP);
a first resistance (R P1 ) coupling the first transistor (Q TN ) to the third transistor (Q BN );
a second resistance (R P2 ) coupling the second transistor (Q TP ) to the fourth transistor (Q BP );
a first capacitance (C F1 ) coupling the first transistor (Q TN ) to a control line of the fourth transistor (Q BP );
a second capacitance (C F2 ) coupling the second transistor (Q TP ) to a control line of the third transistor (Q BN ); and
a controller coupled to the power supply input and configured to generate an enable signal (TX_En);
wherein the driver circuit includes a voltage regulator circuit coupled between the power supply input and both the first transistor (Q TN ) and the second transistor (Q TP ); and
wherein the voltage regulator circuit is configured to couple the first transistor (Q TN ) and the second transistor (Q TP ) to the power supply input (V CC ) if the enable signal (TX_En) is in a first state and to a voltage set by resistor and diode connected devices if the enable signal (TX_En) is in a second state.
2 . The driver circuit of claim 1 :
wherein the controller is configured to detect a ramp-down of a power supply coupled to the power supply input and in response disable a set of circuits in the driver circuit; and
wherein the controller is configured to detect a ramp-up of the power supply a preset time period after the power supply begins the ramp-up.
3 . The driver circuit of claim 1 :
wherein the set of circuits in the driver circuit includes a first set of differential input (IP) switches coupled to the first differential input (IN) and a second set of differential input (IN) switches coupled to the second differential input (IP); and
wherein the first and second differential input switches are configured to couple the first and second differential inputs to a first voltage if the enable signal (TX_En) is in a first state and to a second voltage if the enable signal (TX_En) is in a second state.
4 . The driver circuit of claim 1 :
wherein the controller is configured to generate the enable signal (TX_En) in response to receiving another enable signal (TX_Enable); and
wherein a set of circuits in the driver circuit are configured to receive the enable signal (TX_En) and in response control their operation.
5 . The driver circuit of claim 4 :
wherein the controller includes a POR (power on reset) circuit.
6 . The driver circuit of claim 5 :
wherein the POR circuit has a reset threshold voltage that is higher than a predetermined value for power indication usage.
7 . The driver circuit of claim 5 :
wherein a reset threshold of the POR circuit is configured to detect the ramp-down of the power supply.
8 . The driver circuit of claim 5 :
wherein a reset threshold of the POR circuit is configured to detect a ramp-up of the power supply a preset time period after the power supply begins the ramp-up.
9 . The driver circuit of claim 2 :
wherein the controller is configured to detect the ramp-down of the power supply coupled to the power supply input before the power supply is configured to detect the ramp-down.
10 . The driver circuit of claim 1 :
wherein the driver circuit is embedded in a redriver circuit.
11 . The driver circuit of claim 10 :
wherein the redriver circuit is a voltage-mode redriver circuit.
12 . The driver circuit of claim 1 :
wherein the first differential output (OP) and the second differential output (ON) are configured to be directly connected to a capacitor in-series; and
wherein the first differential input (IP) and the second differential input (IN) are configured to be directly connected to a capacitor in-series.
13 . The driver circuit of claim 1 :
wherein the third transistor (QBN) is configured to be coupled to a load through a first decoupling capacitor (Cex) that is in-series with the first load; and
wherein the fourth transistor (QBP) is configured to be coupled to the load through a second decoupling capacitor (Cex) that is also in-series with the load.
14 . A driver circuit, comprising:
a first transistor (Q TN ) coupled to a first differential input (IN) and a power supply input (VCC);
a second transistor (Q TP ) coupled to a second differential input (IP) and the power supply input;
a third transistor (Q BN ) coupled to a first differential output (ON);
a fourth transistor (Q BP ) coupled to a second differential output (OP);
a first resistance (R P1 ) coupling the first transistor (Q TN ) to the third transistor (Q BN );
a second resistance (R P2 ) coupling the second transistor (Q TP ) to the fourth transistor (QBP);
a first capacitance (C F1 ) coupling the first transistor (Q TN ) to a control line of the fourth transistor (Q BP );
a second capacitance (C F2 ) coupling the second transistor (Q TP ) to a control line of the third transistor (Q BN );
a first switched resistance coupled in parallel with the first capacitance (C F1 );
a second switched resistance coupled in parallel with the second capacitance (C F2 );
a third switched resistance coupling the control line of the third transistor (QBN) to a ground; and
a fourth switched resistance coupling the control line of the fourth transistor (QBP) to the ground.
15 . The driver circuit of claim 14 :
a controller including a first controller sub-circuit coupled to the power supply input; and
wherein the first controller sub-circuit is configured to send an enable signal (SWO_Enable (En 0 )) to the third and fourth switched resistances after a predetermined delay from when a voltage signal at the power supply input ramps-up or ramps-down.
16 . The driver circuit of claim 14 :
wherein the controller includes a second controller sub-circuit coupled to receive an enable signal (TX_En) from the controller; and
wherein the second controller sub-circuit is configured to send an enable signal (SW 1 _Enable (En 1 )) to the first and second switched resistances after a first delay (t 1 ) from when the enable signal (TX_En) transitions from a first state to a second state, and after a second delay (t 2 ) from when the enable signal (TX_En) transitions from the second state to the first state.
17 . The driver circuit of claim 16 :
wherein the second controller circuit is a one-shot circuit.
18 . A driver circuit, comprising:
a first transistor (Q TN ) coupled to a first differential input (IN) and a power supply input (VCC);
a second transistor (Q TP ) coupled to a second differential input (IP) and the power supply input;
a third transistor (Q BN ) coupled to a first differential output (ON);
a fourth transistor (Q BP ) coupled to a second differential output (OP);
a first resistance (R P1 ) coupling the first transistor (Q TN ) to the third transistor (Q BN );
a second resistance (R P2 ) coupling the second transistor (Q TP ) to the fourth transistor (QBP);
a first capacitance (C F1 ) coupling the first transistor (Q TN ) to a control line of the fourth transistor (Q BP );
a second capacitance (C F2 ) coupling the second transistor (Q TP ) to a control line of the third transistor (Q BN ); and
a controller coupled to the power supply input and configured to generate an enable signal (TX_En);
wherein the driver circuit includes a first set of differential input (IP) switches coupled to the first differential input (IN) and a second set of differential input (IN) switches coupled to the second differential input (IP); and
wherein the first and second differential input switches are configured to couple the first and second differential inputs to a first voltage if the enable signal (TX_En) is in a first state and to a second voltage if the enable signal (TX_En) is in a second state.