Digital transmitter featuring a 50%-LO signed phase mapper
Provided herein is a digitally controlled segmented RF power transmitter with a digital processing part and an RF power amplification part having a plurality of segments. The digital processing part has a clock generation block arranged to generate n equi-phased clock signals with a 50% duty-cycle (f LO,x_50% , C x ), and a sign-bit phase mapper unit arranged to receive the n equi-phased clock signals (f LO,x_50% ; C x ), and sign bits (Sign I , Sign Q ), and to output a set of m, m≤n, phase mapped clock signals with a 50% duty-cycle (CLK y,50% ; C y ) using a predetermined phase swapping scheme. Each of the plurality of segments includes logic circuitry receiving the set of m phase-mapped clock signals with a 50% duty-cycle (CLK y,50% ; C y ), and arranged to provide the respective segment driving signal with a duty-cycle z of less than 50%.
1 . A digitally controlled segmented RF power transmitter comprising a digital processing part and an RF power amplification part connected to the digital processing part, the RF power amplification part comprising a plurality of segments, each segment having an associated activation area, the segments being controlled by an activation scheme for activating specific ones of the segments with a segment driving signal depending on a code word received from the digital processing part,
the digital processing part comprising
a clock generation block being arranged to generate n equi-phased clock signals with a 50% duty-cycle, n being an integer value equal to or larger than 4, and
a sign-bit phase mapper unit being arranged to receive the n equi-phased clock signals with the 50% duty-cycle, and to output a set of m, m≤n, phase-mapped clock signals with a 50% duty-cycle,
wherein each of the plurality of segments comprises logic circuitry receiving the set of m phase-mapped clock signals with the 50% duty-cycle, the logic circuitry being arranged to provide the respective segment driving signal with a duty-cycle z of less than 50%.
2 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the logic circuitry is arranged to provide the respective segment driving signal by multiplying predetermined pairs of the set of m phase-mapped clock signals with the 50% duty-cycle.
3 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the logic circuitry comprises symmetrical logic circuit gates.
4 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein n is equal to 4.
5 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the predetermined phase swapping scheme is dependent on the sign bits.
6 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the digital processing part further comprises a delay alignment unit operating on the n equi-phased clock signals with the 50% duty-cycle, the delay alignment unit being connected to inputs of the sign-bit phase mapper unit.
7 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the digital processing part further comprises a clock gating unit connected to outputs of the sign-bit phase mapper unit and arranged to block the m phase-mapped clock signals with the 50% duty-cycle if no predetermined data signal is present in the digital processing part.
8 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein n is equal to 8.
9 . The digitally controlled segmented RF power transmitter according to claim 8 , wherein the logic circuitry is arranged to multiply predetermined pairs of the m phase-mapped clock signals with the 50% duty-cycle to obtain the respective segment driving signal with a duty-cycle of 12.5%.
10 . The digitally controlled segmented RF power transmitter according to claim 8 , wherein the logic circuitry is arranged to multiply predetermined pairs of the m phase-mapped clock signals with the 50% duty-cycle to obtain the respective segment driving signal with a duty-cycle of 25%.
11 . The digitally controlled segmented RF power transmitter according to claim 8 , wherein the logic circuitry is arranged to multiply predetermined pairs of the m phase-mapped clock signals with the 50% duty-cycle to obtain the respective segment driving signal with a duty-cycle of 37.5%.
12 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the plurality of segments are configured for interleaved operation.
13 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the plurality of segments are arranged to provide push-pull output signals.
14 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein the RF power amplification part further comprises circuitry providing complementary signals to drive the plurality of segments.
15 . The digitally controlled segmented RF power transmitter according to claim 1 , wherein a plurality of equi-phased clock signals are used, of which one or more of the plurality of equi-phased clock signals have a frequency which is an integer multiple of another one of the plurality of equi-phased clock signals.