Pointer authentication
In an embodiment, a processor includes hardware circuitry which may be used to detect that a return address has been modified since it was generated. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified return address. In an embodiment, the processor may perform a cryptographic signature operation on the return address to generate a signed return address, and the signature may be verified before the address is used as a return target.
1 . A processor comprising:
one or more registers; and
an execution core coupled to the one or more registers, wherein:
the execution core is configured to execute an instruction to perform a signature operation on a first value to generate a signed value and to store the signed value to a storage location for subsequent use; and
to generate the signed value, the execution core is further configured to perform the signature operation based on a cryptographic key, the value of a stack pointer stored in one of the one or more registers, and an address at which the instruction is stored.
2 . The processor as recited in claim 1 wherein the signature operation is based on the address and an offset specified by the instruction.
3 . The processor as recited in claim 1 wherein the storage location is one of the one or more registers.
4 . The processor as recited in claim 1 wherein the storage location is indicated by the value of the stack pointer.
5 . The processor as recited in claim 1 wherein to store the signed value to the storage location the execution core is configured to store the signed value using a subset of bits of the storage location.
6 . The processor as recited in claim 1 wherein the signed value is a partial portion of an encryption generated from the signature operation on the first value.
7 . The processor as recited in claim 1 wherein the signature operation is based on a block cipher algorithm.
8 . The processor as recited in claim 7 wherein the block cipher algorithm includes one of: advanced encryption standard (AES), data encryption standard (DES), international data encryption algorithm (IDEA), or PRINCE.
9 . The processor as recited in claim 1 wherein to perform the signature operation the execution core is further configured to:
perform a combination or concatenation operation on the first value, the value of the stack pointer, and the address of the instruction to generate a combined value; and
perform the signature operation on the combined value to generate the signed value based on the cryptographic key.
10 . The processor as recited in claim 9 wherein the combination operation is based on an exclusive-OR function.
11 . The processor as recited in claim 1 wherein prior to performing the signature operation the execution core is configured to:
perform a combination operation on the address of the instruction and an offset to generate a combined value; and
perform the signature operation on the combined value to generate the signed value based on the cryptographic key.
12 . The processor as recited in claim 1 wherein the execution core is configured to perform an authenticate operation using the signed value for the subsequent use.
13 . The processor as recited in claim 12 wherein to perform the authenticate operation the execution core is configured to:
obtain a value from the storage location for the subsequent use;
perform a second signature operation on the obtained value to generate a second signed value;
authenticate the obtained value based on the signed value and the second signed value.
14 . The processor as recited in claim 13 wherein to authenticate the obtained value the execution core is configured to determine whether the signed value matches the second signed value based on comparison of the signed value and the second signed value.
15 . The processor as recited in claim 13 wherein the obtained value is a return address for a call to a subroutine that is terminated by one or more return instructions.
16 . The processor as recited in claim 15 wherein the second signature operation is based on the cryptographic key, the value of the stack pointer, and an address of an initial instruction in the subroutine.
17 . The processor as recited in claim 13 wherein the second signature operation is based on the cryptographic key, the value of the stack pointer, and an address at which an instruction corresponding to the authentication operation is stored.
18 . A method comprising:
generating a return address for a call to a subroutine that is terminated by a return instruction;
performing a signature operation on the return address to generate a signed return address, wherein the signature operation is based on a cryptographic key, a value of a stack pointer, and an address of an initial instruction in the subroutine;
detecting an attempt to use the signed return address by the return instruction;
authenticating the return instruction based on the signed address responsive to detecting the attempt; and
preventing the return due to a failure in authenticating the return instruction.
19 . The method as recited in claim 18 wherein authenticating the signed address responsive to detecting the attempt comprises:
obtaining an address for the return instruction;
performing a second signature operation on the obtained address to generate a second signed return address, wherein the second signature operation is based on the cryptographic key, the value of a stack pointer, and an address of the return instruction; and
authenticating the return instruction based on comparison of the signed address and the second signed address.
20 . The method as recited in claim 18 further comprising:
prior to performing the signature operation,
performing a combination operation on the return address, the value of the stack pointer, and the address of the initial instruction to generate a combined value; and
performing the signature operation on the combined value to generate the signed value based on the cryptographic key.