Integrated circuit device
An integrated circuit device includes a substrate having a plurality of active regions defined therein, a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, and crossing a first active region of the plurality of active regions, a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure, and crossing the first active region, a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer, and a bit line contacting the direct contact.
1 . An integrated circuit device comprising:
a substrate having a plurality of active regions defined therein;
a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, the first word line structure extending in a first horizontal direction, and the first word line structure crossing a first active region of the plurality of active regions;
a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure in a second horizontal direction that crosses the first horizontal direction, the second word line structure extending in the first horizontal direction, and the second word line structure crossing the first active region;
a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer; and
a bit line extending in the second horizontal direction and contacting the direct contact.
2 . The integrated circuit device of claim 1 , wherein the first word line structure further includes an insulating barrier film covering a side wall of the oxide semiconductor channel layer.
3 . The integrated circuit device of claim 2 , wherein the insulating barrier film includes aluminum oxide.
4 . The integrated circuit device of claim 1 , wherein the first word line structure further includes a conductive capping layer on the oxide semiconductor channel layer, the conductive capping layer being separated from the first word line by the oxide semiconductor channel layer in a vertical direction.
5 . The integrated circuit device of claim 4 , wherein the direct contact is in contact with the conductive capping layer.
6 . The integrated circuit device of claim 4 , wherein the conductive capping layer includes doped polysilicon.
7 . The integrated circuit device of claim 1 , wherein the direct contact overlaps with the first word line in a vertical direction.
8 . The integrated circuit device of claim 1 , further comprising:
a plurality of capacitor contacts respectively contacting the plurality of active regions;
a first capacitor structure extending in the substrate in a vertical direction, the first capacitor structure being at a lower level than the first word line structure in the vertical direction and the first capacitor structure being connected to the oxide semiconductor channel layer; and
a second capacitor structure extending on the substrate in the vertical direction, the second capacitor structure being at a higher level than the second word line structure in the vertical direction, and the second capacitor structure being connected to a capacitor contact of the plurality of capacitor contacts.
9 . The integrated circuit device of claim 8 , wherein the plurality of capacitor contacts include a first capacitor contact and a second capacitor contact, the first capacitor contact being in contact with the first active region, and the second capacitor contact being separated from the first active region in the first horizontal direction and the second capacitor contact being in contact with a second active region adjacent to the first active region, wherein the second capacitor contact overlaps with the first word line structure in the vertical direction.
10 . The integrated circuit device of claim 1 , wherein the first word line structure further includes an insulating capping layer covering a top surface of the oxide semiconductor channel layer.
11 . An integrated circuit device comprising:
a substrate having a plurality of active regions defined therein;
a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, the first word line structure extending in a first horizontal direction, and the first word line structure crossing a first active region of the plurality of active regions;
a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure in a second horizontal direction that crosses the first horizontal direction, the second word line structure extending in the first horizontal direction, and the second word line structure crossing the first active region;
a first capacitor structure buried in the substrate and connected to the first word line structure, the first capacitor structure being at a lower vertical level than the first word line structure; and
a second capacitor structure on the substrate and connected to the second word line structure.
12 . The integrated circuit device of claim 11 , further comprising:
a direct contact partially passing through the first word line structure and the first active region and contacting the oxide semiconductor channel layer.
13 . The integrated circuit device of claim 12 , wherein
the first word line structure further includes a barrier film surrounding a side wall and a top surface of the oxide semiconductor channel layer, and
the direct contact passes through the barrier film.
14 . The integrated circuit device of claim 12 , wherein the first word line structure further includes a conductive capping layer over the first word line, the conductive capping layer being separated from the first word line by the oxide semiconductor channel layer.
15 . The integrated circuit device of claim 14 , wherein the direct contact is in contact with the conductive capping layer.
16 . The integrated circuit device of claim 11 , wherein the oxide semiconductor channel layer includes indium-gallium-zinc oxide (IGZO).
17 . An integrated circuit device comprising:
a substrate having a plurality of active regions defined therein;
a plurality of first word line structures each including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the plurality of first word line structures being buried in the substrate, the plurality of first word line structures extending in a first horizontal direction, and the plurality of first word line structures crossing some of the plurality of active regions;
a plurality of second word line structures each including a second word line and a second gate dielectric film surrounding the second word line, the plurality of second word line structures being buried in the substrate and separated from each of the plurality of first word line structures in a second horizontal direction that crosses the first horizontal direction, the plurality of second word line structures extending in the first horizontal direction, and the plurality of second word line structures crossing some of the plurality of active regions;
a plurality of first capacitor structures buried in the substrate and respectively connected to the plurality of first word line structures, the plurality of first capacitor structures being at a lower vertical level than the plurality of first word line structures;
a plurality of second capacitor structures on the substrate and respectively connected to the plurality of second word line structures;
a plurality of direct contacts partially passing through the plurality of active regions, respectively, and the plurality of first word line structures, respectively, each of the plurality of direct contacts being in contact with the oxide semiconductor channel layer; and
a plurality of capacitor contacts respectively contacting the plurality of active regions.
18 . The integrated circuit device of claim 17 , wherein
the plurality of capacitor contacts include a first capacitor contact and a second capacitor contact, the first capacitor contact being in contact with a first active region of the plurality of active regions, and the second capacitor contact being separated from the first active region in the first horizontal direction and being in contact with a second active region adjacent to the first active region, and
the second capacitor contact vertically overlaps with a first word line structure crossing the first active region among the plurality of first word line structures.
19 . The integrated circuit device of claim 17 , wherein each of the plurality of first word line structures further includes a barrier film covering a side wall of the oxide semiconductor channel layer.
20 . The integrated circuit device of claim 17 , wherein
each of the plurality of first word line structures further includes a conductive capping layer covering a top surface of the oxide semiconductor channel layer, and
the conductive capping layer is in contact with a direct contact of the plurality of direct contacts.