Granted Patent B2

US 12,563,976 · App. 17/940,857 · Granted Feb 24, 2026

Inventor: Gwang Hyuk Shin (Icheon-si, KR)

Assignee: SK HYNIX INC.

H10N50/80H10B61/10H10N50/01

Abstract

Claims (37)

1 . A semiconductor device comprising:

first conductive lines;

second conductive lines disposed on the first conductive lines to be spaced apart from the first conductive lines;

selector layer disposed between the first conductive lines and the second conductive lines;

a variable resistance layer disposed between the first conductive lines and the second conductive lines; and

a first electrode layer including graphene and disposed between the variable resistance layer and the selector layer,

wherein the graphene has a multilayer structure with two to seven layers.

2 . The semiconductor device according to claim 1 , wherein the first electrode layer is configured to physically isolate the variable resistance layer and the selector layer from each other and electrically connect the variable resistance layer and the selector layer to each other.

3 . The semiconductor device according to claim 1 , wherein the selector layer is disposed between the first conductive line and the first electrode layer, and the variable resistance layer is disposed between the first electrode layer and the second conductive line.

4 . The semiconductor device according to claim 1 , further comprising:

a second electrode layer disposed between the first conductive line and the selector layer; and

a third electrode layer disposed between the variable resistance layer and the second conductive line.

5 . The semiconductor device according to claim 4 , wherein the first electrode layer has a smaller thickness than at least one of the second electrode layer or the third electrode layer.

6 . The semiconductor device according to claim 4 , wherein the first electrode layer has a lower surface roughness than at least one of the second electrode layer or the third electrode layer.

7 . The semiconductor device according to claim 1 , further comprising a hard mask pattern disposed between the variable resistance layer and the second conductive line.

8 . A method for fabricating a semiconductor device comprising:

forming a first conductive line;

forming a selector layer over the first conductive line;

forming a first electrode layer that includes graphene over the selector layer;

forming a variable resistance layer; and

forming a second conductive line over the variable resistance layer,

wherein the graphene has a multilayer structure with two to seven layers.

9 . The method according to claim 8 , wherein the selector layer is disposed between the first conductive line and the first electrode layer, and the variable resistance layer is disposed between the first electrode layer and the second conductive line.

10 . The method according to claim 8 , further comprising:

forming a hard mask pattern over the variable resistance layer,

wherein the selector layer, the first electrode layer and the variable resistance layer are stacked by etching the variable resistance layer, the first electrode layer and the selector layer using the hard mask pattern.

11 . The method according to claim 8 , further comprising:

forming a second electrode layer after forming the first conductive line and before forming the selector layer, wherein the second electrode layer is disposed between the first conductive line and the selector layer; and

forming a third electrode layer after forming the variable resistance layer and before forming the second conductive line, wherein third electrode layer is disposed between the variable resistance layer and the second conductive line.

12 . The method according to claim 11 , wherein the first electrode layer has a smaller thickness than at least one of the second electrode layer or the third electrode layer.

13 . The method according to claim 11 , wherein the first electrode layer has a lower surface roughness than at least one of the second electrode layer or the third electrode layer.

14 . The method according to claim 8 , wherein the forming of the first electrode layer comprises:

forming a graphene layer on a metal layer formed over a substrate by performing a chemical vapor deposition (CVD);

forming a support layer on the graphene layer;

separating the metal layer, the graphene layer and the support layer from the substrate to remove the substrate;

separating the graphene layer and the support layer from the metal layer to remove the metal layer; and

transferring the graphene layer to the selector layer.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (18)