Granted Patent B2

US 12,564,908 · App. 17/200,168 · Granted Mar 3, 2026

Inventors: Sergio V. Martinez (Sahuarita, AZ); Jeffrey R. Ogorzalek (Attleboro, MA); Patrick J. Lott (Lowell, MA)

Assignee: RAYTHEON COMPANY

B23K37/06B23K1/0016B23K3/0638H05K3/323H05K3/3436B23K2101/42H05K2203/0126

Abstract

Claims (7)

1 . A substrate of an electronic assembly comprising:

a solder paste comprising a metal in a deposition pattern within a pad area of the substrate, the deposition pattern comprising an array of discrete domains of the solder paste comprising the metal that extends across the pad area of the substrate with regular spacings of about 0.076 to about 0.203 millimeters (mm) between the discrete domains, the deposition pattern comprising the array of discrete domains has a tangency with respect to an edge of the pad area of about 0.025 mm to about 0.127 mm;

wherein the pad area comprises palladium or a palladium alloy.

2 . The substrate of claim 1 , wherein a pitch of the array of discrete domains is about 0.254 to about 1.27 millimeters (mm).

3 . The substrate of claim 1 , wherein the substrate is a bottom termination component or microcircuit.

4 . The substrate of claim 1 , wherein the solder paste includes lead (Pb).

5 . The substrate of claim 1 , wherein the solder paste is tin-lead (SnPb), tin-lead-silver (SnPbAg), tin-silver-copper (SnAgCu), tin-silver-bismuth (SnAgBi), tin-bismuth (SnBi), tin-indium (SnIn), or any combination thereof.

Assignments (1)

Continuity (2)

References Cited (72)