Method for mask data synthesis with wafer target adjustment
A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.
1 . A method for manufacturing a lithographic mask for an integrated circuit, comprising:
generating a database, comprising:
generating a plurality of integrated circuit layout patterns;
performing mask projection of each one of the integrated circuit layout patterns to generate a corresponding pattern; and
storing the integrated circuit layout patterns and the corresponding patterns in the database stored in a storage memory;
training a convolutional neural network based on a first portion of the database,
wherein the integrated circuit layout patterns are inputs of the convolutional neural network and the corresponding patterns are outputs of the convolutional neural network;
verifying the convolutional neural network based on a remaining second portion of the database;
receiving a first integrated circuit layout pattern;
generating, as an output of the convolutional neural network and based on the first integrated circuit layout pattern, a first pattern resulting from when the first integrated circuit layout pattern is projected on a wafer; and
inspecting the first pattern to verify the first integrated circuit layout pattern.
2 . The method of claim 1 , wherein the generated first pattern comprises one or more parameters of the first pattern, and wherein the verifying the first integrated circuit layout pattern further comprises:
verifying the one or more parameters are within a process window, wherein the process window comprises a threshold range of radiation energy for generating the first pattern and a depth of focus threshold range for the generated first pattern.
3 . The method of claim 2 , further comprising:
performing two or more mask projections for each one of a plurality of first integrated circuit layout patterns to generate two or more corresponding patterns for each one of the first integrated circuit layout patterns, wherein the two or more mask projections have different exposure doses and different depth of focus conditions.
4 . The method of claim 3 , wherein the first integrated circuit layout pattern comprises a corresponding exposure dose and a corresponding depth of focus for generating the first integrated circuit layout pattern, the method further comprising:
verifying the corresponding exposure dose and the corresponding depth of focus are within the process window.
5 . The method of claim 1 , wherein the verifying the first integrated circuit layout pattern does not generate defects when verifying a probability of generating a defect in the first pattern is below a first threshold level.
6 . The method of claim 1 , wherein first integrated circuit layout pattern comprises a graphic design system (GDS) file.
7 . The method of claim 1 , wherein the performing the mask projection is a simulation projection.
8 . The method of claim 1 , further comprising:
performing an optical proximity correction (OPC) process and an inverse lithographic technology (ILT) process to the first integrated circuit layout pattern to produce an OPC-ILT-enhanced mask layout; and
verifying the OPC-ILT-enhanced mask layout using the convolutional neural network.
9 . The method of claim 1 , wherein the inspecting the first pattern comprises:
verifying that the first pattern does not generate defects.
10 . The method of claim 1 , comprising:
performing an optical proximity correction to a mask layout corresponding to the integrated circuit to produce a corrected mask layout;
performing an inverse lithographic technology process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout;
generating, by the convolutional neural network, a second pattern based on the OPC-ILT-enhanced mask layout, when the OPC-ILT-enhanced mask layout is projected on the wafer; and
inspecting the second pattern to verify that the second pattern does not have defects,
wherein generating the second pattern comprises a generating a corresponding exposure dose and a corresponding depth of focus for generating the lithographic mask.
11 . The method of claim 10 , further comprising:
training the convolutional neural network using a training data set comprising OPC-ILT-enhanced mask layouts stored in the first portion of the database; and
verifying the convolutional neural network using a verification data set comprising patterns associated with the OPC-ILT-enhanced mask layouts stored in the remaining second portion of the database.
12 . The method of claim 11 , wherein training the convolutional neural network further comprises:
generating a plurality of OPC-ILT-enhanced mask layouts;
providing the plurality of OPC-ILT-enhanced mask layouts as inputs to the convolutional neural network;
receiving output patterns corresponding to the of plurality of OPC-ILT-enhanced mask layouts as output from the convolutional neural network; and
storing the plurality of OPC-ILT-enhanced mask layouts and the output patterns in the first portion of the database.
13 . The method of claim 11 , wherein verifying the convolutional neural network comprises:
confirming that for each record of the training data set, a squared error between an integrated circuit layout of the verification data set and a corresponding output of the convolutional neural network, based on to a corresponding OPC-ILT-enhanced mask layout of a same record, is below a threshold level.
14 . A method for manufacturing a lithographic mask for an integrated circuit, comprising:
generating a plurality of integrated circuit layout patterns;
performing mask projection of each one of the integrated circuit layout patterns to generate a corresponding pattern;
storing the integrated circuit layout patterns and the corresponding patterns in a database stored in a memory;
training a convolutional neural network using a training data set stored in the database;
verifying the convolutional neural network using a verification data set stored in the database;
generating, as an output of the convolutional neural network and based on a first integrated circuit layout pattern, a first pattern resulting from when the first integrated circuit layout pattern is projected on a wafer;
performing an optical proximity correction (OPC) process and an inverse lithographic technology (ILT) process to the first integrated circuit layout pattern to produce an OPC-ILT-enhanced mask layout; and
verifying the OPC-ILT-enhanced mask layout using the convolutional neural network.
15 . The method of claim 14 , further comprising receiving the integrated circuit layout patterns from a mask design module.
16 . The method of claim 14 , further comprising storing the OPC-ILT-enhanced mask layout in the database stored in the memory.
17 . The method of claim 16 , further comprising training the convolutional neural network based on the database stored in the memory.
18 . The method of claim 14 , wherein the first integrated circuit layout pattern comprises a graphic design system (GDS) file, and wherein the OPC-ILT-enhanced mask layout comprises an adjusted GDS file.
19 . The method of claim 14 , wherein the performing the mask projection is a simulation projection.
20 . The method of claim 14 , wherein the first integrated circuit layout pattern comprises a corresponding exposure dose and a corresponding depth of focus for generating the first integrated circuit layout pattern, the method further comprising:
verifying the corresponding exposure dose and the corresponding depth of focus are within a process window.