Systems and methods for timestep shared memory multiprocessing based on tracking table mechanisms
Provided are systems, methods, and apparatuses for timestep shared memory multiprocessing based on tracking table mechanisms. In one or more examples, the systems, devices, and methods include determining a first node writes application data to a memory, obtaining a data address of the memory associated with the application data, and generating an index of the data address based on hashing the data address in a hash function. In one or more examples, the systems, devices, and methods include generating a tracking entry based on the first node writing application data to the memory, storing the index and the tracking entry in a bucket of a hash table, and detecting an access violation to the application data based on the tracking entry indicating a node other than the first node modifies the application data.
1 . A method comprising:
determining a first node writes application data to a memory;
obtaining a data address of the memory associated with the application data;
generating an index of the data address based on hashing the data address in a hash function;
generating a tracking entry based on the first node writing application data to the memory;
storing the index and the tracking entry in a bucket of a hash table; and
detecting an access violation to the application data based on the tracking entry indicating a node other than the first node modifies the application data.
2 . The method of claim 1 , wherein the tracking entry includes an identifier of the first node, indicating the first node wrote the application data to the memory.
3 . The method of claim 1 , further comprising monitoring the application data based on a timestep, wherein the application data is written within a time period of the timestep.
4 . The method of claim 3 , further comprising detecting, based on the tracking entry, an access violation when a node other than the first node modifies the application data during the timestep.
5 . The method of claim 1 , wherein the application data comprises floating point data of a force, a velocity, an acceleration, or a position of an object.
6 . The method of claim 1 , wherein:
the memory is a memory of a system on chip (SoC), the SoC including the first node or a second node different from the first node, and
the data address is obtained from a logical circuit of the SoC.
7 . The method of claim 1 , further comprising storing a write pointer to a first configuration status register, the write pointer pointing to a next available bucket of the hash table.
8 . The method of claim 1 , further comprising:
storing a start of allocation to a second configuration status register; and
storing an end of allocation to a third configuration status register, wherein the start of allocation points to a starting bucket of the hash table and the end of allocation point to an ending bucket of the hash table.
9 . The method of claim 1 , further comprising adding a collision heap allocation based on determining a fill threshold of the hash table is satisfied.
10 . The method of claim 9 , further comprising:
identifying a collision associated with a second bucket of the hash table;
storing a second index and a second tracking entry in a bucket of the collision heap allocation; and
linking the second bucket of the hash table to the bucket of the collision heap allocation.
11 . A device comprising:
a memory; and
at least one processor coupled with the memory configured to:
determine a first node writes application data to the memory;
obtain a data address of the memory associated with the application data;
generate an index of the data address based on hashing the data address in a hash function;
generate a tracking entry based on the first node writing application data to the memory;
store the index and the tracking entry in a bucket of a hash table; and
detect an access violation to the application data based on the tracking entry indicating a node other than the first node modifies the application data.
12 . The device of claim 11 , wherein the tracking entry includes an identifier of the first node, indicating the first node wrote the application data to the memory.
13 . The device of claim 11 , wherein the at least one processor is configured to monitor the application data based on a timestep, wherein the application data is written within a time period of the timestep.
14 . The device of claim 13 , wherein the at least one processor is configured to detect, based on the tracking entry, an access violation when a node other than the first node modifies the application data during the timestep.
15 . The device of claim 11 , wherein the application data comprises floating point data of a force, a velocity, an acceleration, or a position of an object.
16 . The device of claim 11 , wherein:
the memory is a memory of a system on chip (SoC), the SoC including the first node or a second node different from the first node, and
the data address is obtained from a logical circuit of the SoC.
17 . The device of claim 11 , wherein the at least one processor is configured to store a write pointer to a first configuration status register, the write pointer pointing to a next available bucket of the hash table.
18 . A non-transitory computer-readable medium storing code that comprises instructions executable by a processor of a system on chip (SoC) to:
determine a first node writes application data to a memory;
obtain a data address of the memory associated with the application data;
generate an index of the data address based on hashing the data address in a hash function;
generate a tracking entry based on the first node writing application data to the memory;
store the index and the tracking entry in a bucket of a hash table; and
detect an access violation to the application data based on the tracking entry indicating a node other than the first node modifies the application data.
19 . The non-transitory computer-readable medium of claim 18 , wherein the tracking entry includes an identifier of the first node, indicating the first node wrote the application data to the memory.
20 . The non-transitory computer-readable medium of claim 18 , wherein the code includes further instructions executable by the processor to cause the SoC to monitor the application data based on a timestep, wherein the application data is written within a time period of the timestep.