Data driving circuit and a display device including the same
A data driving circuit including: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line.
1 . A display device, comprising:
a display panel including a plurality of pixels connected to a plurality of data lines; and
a data driving circuit which receives an output image signal and provides a plurality of data signals to the plurality of data lines, and
wherein the data driving circuit includes:
a latch which receives the output image signal and outputs a plurality of latch data signals each including a plurality of bits;
a transition detector which compares the plurality of latch data signals of a current line with the plurality of latch data signals of a previous line, respectively, and outputs a first transition detection signal based on the comparison;
a delay compensator which outputs a plurality of delay data signals obtained by delaying some of the plurality of bits of each of the plurality of latch data signals based on the first transition detection signal;
a level shifter which outputs a plurality of level shift data signals obtained by changing a voltage level of each of the plurality of delay data signals; and
an output circuit which converts the plurality of level shift data signals into the plurality of data signals and provides the plurality of data signals obtained by converting the plurality of level shift data signals to the plurality of data lines,
wherein the delay compensator counts a number of the first transition detection signal having a first value in the current line and outputs the delay data signal obtained by delaying some of the plurality of bits of each of the plurality of latch data signals when the counted number is greater than a first reference value.
2 . The display device of claim 1 , wherein the transition detector outputs the first transition detection signal as the first value when a latch data signal of the current line and a latch data signal of the previous line corresponding to each of the data lines among the plurality of latch data signals of the current line and the plurality of latch data signals of the previous line correspond to a first pattern.
3 . The display device of claim 2 , wherein the delay compensator includes:
a counter which counts the number of the first transition detection signal having the first value in the current line, and outputs a first count signal based on the counted number;
a delay controller which outputs a control signal when the first count signal is greater than the first reference value; and
a plurality of delay circuits which respectively correspond to the plurality of latch data signals, and
wherein each of the plurality of delay circuits includes a plurality of delays which respectively correspond to the plurality of bits of a corresponding latch data signal of the plurality of latch data signals, and outputs the delay data signal obtained by delaying some of the plurality of bits of the corresponding latch data signal in response to the control signal.
4 . The display device of claim 3 , wherein each of the plurality of delay circuits includes delays which output the delay data signal by delaying some of lower bits of the plurality of bits of the corresponding latch data signal in response to the control signal.
5 . The display device of claim 4 , wherein each of the plurality of delay circuits outputs the delay data signal by delaying a most significant bit of the plurality of bits of the corresponding latch data signal in response to the control signal.
6 . The display device of claim 4 , wherein each of the plurality of delay circuits outputs the delay data signal by delaying remaining bits except for a most significant bit of the plurality of bits of the corresponding latch data signal in response to the control signal.
7 . The display device of claim 1 , wherein the transition detector:
outputs the first transition detection signal as a first value when the plurality of latch data signals of the current line and the plurality of latch data signals of the previous line correspond to a first pattern, and
outputs a second transition detection signal as the first value when the plurality of latch data signals of the current line and the plurality of latch data signals of the previous line correspond to a second pattern.
8 . A display device, comprising:
a display panel including a plurality of pixels connected to a plurality of data lines; and
a data driving circuit which receives an output image signal and provides a plurality of data signals to the plurality of data lines, and
wherein the data driving circuit includes:
a latch which receives the output image signal and outputs a plurality of latch data signals each including a plurality of bits;
a transition detector which compares the plurality of latch data signals of a current line with the plurality of latch data signals of a previous line, respectively, and outputs a first transition detection signal based on the comparison;
a delay compensator which outputs a plurality of delay data signals obtained by delaying some of the plurality of bits of each of the plurality of latch data signals based on the first transition detection signal;
a level shifter which outputs a plurality of level shift data signals obtained by changing a voltage level of each of the plurality of delay data signals; and
an output circuit which converts the plurality of level shift data signals into the plurality of data signals and provides the plurality of data signals obtained by converting the plurality of level shift data signals to the plurality of data lines,
wherein the delay compensator includes:
a counter which counts a number of the first transition detection signal having a first value in the current line to output a first count signal, and counts a number of a second transition detection signal having the first value to output a second count signal;
a delay controller which outputs a control signal based on a difference value between the first count signal and the second count signal; and
a plurality of delay circuits which respectively correspond to the plurality of latch data signals, and
wherein each of the plurality of delay circuits includes a plurality of delays which respectively correspond to the plurality of bits of a corresponding latch data signal of the plurality of latch data signals, and outputs the delay data signal obtained by delaying some of the plurality of bits of the corresponding latch data signal in response to the control signal, and
wherein the delay controller outputs the control signal such that some of the plurality of bits of the corresponding latch data signal are delayed when an absolute value of the difference value is greater than a reference value.
9 . The display device of claim 8 , wherein the delay controller outputs the control signal such that some of the plurality of bits each of the plurality of latch data signals are delayed when an absolute value of the difference value is greater than a reference value.
10 . The display device of claim 9 , wherein the delay circuit outputs the delay data signal by delaying remaining bits except for a most significant bit of the plurality of bits of each of the plurality of latch data signals in response to the control signal.
11 . The display device of claim 10 , wherein the delay circuit outputs the delay data signal by delaying a most significant bit of the plurality of bits of each of the plurality of latch data signals in response to the control signal.