IP Library Granted Patent US 12,575,178
Granted Patent B2
US 12,575,178 · App. 17/524,198 · Granted Mar 10, 2026

Front end integrated circuits incorporating differing silicon-on-insulator technologies

Inventors: Hailing Wang (Acton, MA); Guillaume Alexandre Blin (Carlisle, MA); David Scott Whitefield (Andover, MA)
Assignee: SKYWORKS SOLUTIONS, INC.
H01L27/1203H01L21/84H01L29/7838H03F3/213H03F2200/294
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Quick Facts
Patent No.
US 12,575,178
App. No.
17/524,198
Granted
Mar 10, 2026
Kind
B2
Abstract

SOI-based technology platforms are described that provide fully integrated front end integrated circuits (FEICs) that include switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick film region of the integrated circuit, resulting in a partially depleted silicon-on-insulator (PDSOI) PA, and the switches and LNAs can be built in a thin film region of the integrated circuit, resulting in fully depleted silicon-on-insulator (FDSOI) switches and LNAs. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film region, the thin film region, or both regions.

Claims (9)

1 . A front end integrated circuit comprising:

a substrate;

an insulator layer on top of the substrate; and

a semiconductor layer on top of the insulator layer, the semiconductor layer forming a thin film region and a thick film region, the thin film region including one or more fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) devices and one or more FDSOI switch devices, the thick film region including one or more partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) devices, the semiconductor layer in the thin film region being at least 5 nm thick and less than or equal to 50 nm thick and the semiconductor layer in the thick film region being at least about 50 nm thick and less than or equal to 180 nm thick.

2 . The front end integrated circuit of claim 1 wherein the insulator layer is at least 100 nm thick.

3 . The front end integrated circuit of claim 1 wherein the insulator layer is a buried oxide layer.

4 . The front end integrated circuit of claim 1 wherein the semiconductor layer in the thin film region is ¼ of a gate length of the one or more FDSOILNA devices.

5 . The front end integrated circuit of claim 1 wherein the thin film region of the semiconductor layer is formed using local thinning.

6 . The front end integrated circuit of claim 1 wherein the thick film region of the semiconductor layer is formed using selective epitaxial growth.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2022
From: WANG, HAILING; BLIN, GUILLAUME ALEXANDRE; WHITEFIELD, DAVID SCOTT
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 059980/0172 →
Continuity (2)
Provisional Application 63112951 · Nov 12, 2020
Related Publication 20220254812A1 · Aug 11, 2022
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