Wiring board and semiconductor package
A semiconductor package includes a wiring board including at least one pair of connection structures electrically connecting at least one pair of differential signal transmission lines and at least one pair of differential signal transmission terminals, respectively. The at least one pair of connection structures includes first via structures staggered in a vertical direction, at least one first connection line electrically connecting the first via structures, second via structures staggered in the vertical direction, and at least one second connection line electrically connecting the second via structures. The at least one first connection line is spaced apart from the at least one second connection line in the vertical direction and electrically insulated therefrom, and intersects the at least one second connection line in the vertical direction.
1 . A semiconductor package comprising:
a wiring board having an upper surface and a lower surface opposing each other, at least a first pair of differential signal transmission lines disposed on the upper surface, at least a first pair of differential signal transmission terminals disposed below the lower surface, and at least a first pair of connection structures electrically connecting each line of the first pair of differential signal transmission lines to each terminal of the first pair of differential signal transmission terminals, respectively;
a semiconductor chip disposed on the upper surface of the wiring board; and
external connection bumps disposed below the lower surface of the wiring board to correspond to the first pair of differential signal transmission terminals, respectively,
wherein the first pair of connection structures includes first via structures disposed to be staggered along a vertical direction with respect to the lower surface, at least one first connection line electrically connecting the first via structures, second via structures staggered along the vertical direction, and at least one second connection line electrically connecting the second via structures, and
the at least one first connection line is spaced apart from the at least one second connection line in the vertical direction and is electrically insulated therefrom, and crosses the at least one second connection line when viewed from the vertical direction.
2 . The semiconductor package of claim 1 , wherein:
the first via structures and the at least one first connection line form a first differential signal line of the first pair of differential signal transmission lines, the first differential signal line including at least a portion having a square wave shape formed parallel to a first plane,
the second via structures and the at least one second connection line form a second differential signal line of the first pair of differential signal transmission lines, the second differential signal line including at least a portion having a square wave shape formed parallel to the first plane or a second plane, and
the first plane and second plane extend in the vertical direction.
3 . The semiconductor package of claim 2 , wherein the first plane and the second plane intersect each other.
4 . The semiconductor package of claim 1 , wherein the first pair of differential signal transmission lines are cross-connected to the first pair of differential signal transmission terminals.
5 . The semiconductor package of claim 1 , wherein at least some of the first via structures and the second via structures are positioned between the first pair of differential signal transmission terminals, when viewed from the vertical direction.
6 . The semiconductor package of claim 1 , wherein at least some of the first via structures and the second via structures do not overlap either differential signal transmission terminal of the first pair of differential signal transmission terminals in the vertical direction.
7 . The semiconductor package of claim 1 , wherein each via structure of the first via structures and each via structure of the second via structures includes one via layer or includes two via layers stacked in the vertical direction.
8 . A semiconductor package comprising:
a wiring board having an upper surface and a lower surface opposing each other, the wiring board including at least a first pair of signal transmission lines disposed on the upper surface, at least a first pair of signal transmission terminals disposed below the lower surface, and a first pair of connection structures electrically connecting the first pair of signal transmission lines to the first pair of signal transmission terminals;
a semiconductor chip disposed on the upper surface of the wiring board; and
external connection bumps disposed below the lower surface of the wiring board to correspond to the first pair of signal transmission terminals, respectively,
wherein the first pair of connection structures includes a first connection structure connecting one signal transmission line of the first pair of signal transmission lines to one signal transmission terminal of the first pair of signal transmission terminals and including first via structures alternately disposed and electrically connected to each other on a first axis and a second axis extending in a vertical direction with respect to the lower surface and spaced apart from each other in a horizontal direction with respect to the lower surface, and disposed between the first pair of signal transmission terminals when viewed from the vertical direction, and a second connection structure connecting the other signal transmission line of the first pair of signal transmission lines to the other signal transmission terminal of the first pair of signal transmission terminals and including second via structures alternately disposed and electrically connected to each other on a third axis and a fourth axis extending in the vertical direction and spaced apart from each other in the horizontal direction, and disposed between the first pair of signal transmission terminals without overlapping either signal transmission terminal of the first pair of signal transmission terminals when viewed from the vertical direction.
9 . The semiconductor package of claim 8 , wherein the first connection structure includes a first connection line connecting a first via structure disposed on the first axis and a first via structure disposed on the second axis, and the second connection structure includes a second connection line connecting a second via structure disposed on the third axis and a second via structure disposed on the fourth axis.
10 . The semiconductor package of claim 9 , wherein the first axis, the second axis, the third axis, and the fourth axis are disposed such that the first connection line and the second connection line cross each other when viewed from the vertical direction.
11 . The semiconductor package of claim 10 , wherein the first connection line and the second connection line are located at different vertical levels.
12 . The semiconductor package of claim 9 , wherein the first axis, the second axis, the third axis, and the fourth axis are disposed such that the first connection line and the second connection line do not cross each other when viewed from the vertical direction.
13 . The semiconductor package of claim 8 , wherein:
each of the first via structures includes at least one first via layer overlapping the first axis or the second axis, and
each of the second via structures includes at least one second via layer overlapping the third axis or the fourth axis.
14 . The semiconductor package of claim 8 , wherein at least one of the first via structures includes two or more consecutive via layers stacked along one of the first axis or the second axis and at least one of the second via structures includes two or more consecutive via layers stacked along one of the third axis or the fourth axis.
15 . The semiconductor package of claim 8 , wherein the first axis, the second axis, the third axis, and the fourth axis do not overlap either signal transmission terminal of the first pair of signal transmission terminals in the vertical direction.
16 . The semiconductor package of claim 8 , wherein:
the first axis is disposed closer to the first pair of signal transmission lines than the second axis, and
the third axis is disposed closer to the first pair of signal transmission lines than the fourth axis.
17 . The semiconductor package of claim 8 , wherein a distance between the first pair of signal transmission terminals is greater than a distance between the first pair of signal transmission lines.
18 . A semiconductor package comprising:
a wiring board having an upper surface and a lower surface opposing each other, and including at least a first pair of signal transmission lines disposed on the upper surface, at least a first pair of signal transmission terminals disposed below the lower surface, and a first pair of connection structures, crossing each other when viewed from a vertical direction perpendicular to the upper surface of the wiring board, and respectively electrically connecting one signal transmission line of the first pair of signal transmission lines to one signal transmission terminal of the first pair of signal transmission terminals, and the other signal transmission line of the first pair of signal transmission lines to the other signal transmission terminal of the first pair of signal transmission terminals; and
a semiconductor chip disposed on the upper surface of the wiring board.
19 . The semiconductor package of claim 18 , wherein at least a portion of the first pair of connection structures does not overlap either signal transmission terminal of the first pair of signal transmission terminals in a direction perpendicular to the lower surface.
20 . The semiconductor package of claim 18 , wherein each connection structure of the first pair of connection structures includes via structures disposed to be staggered along a direction perpendicular to the lower surface.