Semiconductor assembly having dual conduction channels for electricity and heat passage
A semiconductor assembly includes a top substrate and a base substrate attached to top and bottom electrode layers of a semiconductor device, respectively. The top substrate includes an electrode connection plate thermally conductible with and electrically connected to the top electrode layer of the semiconductor device and vertical posts protruding from the electrode connection plate and electrically connected to the base substrate. The base substrate includes an electrode connection slug embedded in a dielectric layer and thermally conductible with and electrically connected to the bottom electrode layer of the semiconductor device and first and second routing circuitries deposited on two opposite surfaces of the dielectric layer, respectively, and electrically connected to each other.
1 . A semiconductor assembly, comprising a top substrate, a base substrate and a semiconductor device, wherein:
the top substrate includes an electrode connection plate, a plurality of vertical posts protruding from a substantially planar inner surface of the electrode connection plate, and a flatness control layer on a substantially planar outer surface of the electrode connection plate opposite to the substantially planar inner surface, wherein the top substrate is electrically connected to the base substrate using a first soldering material between the vertical posts and the base substrate and the inner surface of the electrode connection plate provides a first conduction surface for electrical and thermal conduction with the semiconductor device;
the base substrate includes a dielectric layer, an electrode connection slug, a first routing circuitry on a substantially planar first surface of the dielectric layer, and a second routing circuitry on an opposite substantially planar second surface of the dielectric layer, wherein the electrode connection slug is embedded in the dielectric layer and provides a second conduction surface for electrical and thermal conduction with the semiconductor device, and the first routing circuitry and the second routing circuitry are electrically connected to each other; and
the semiconductor device includes a first electrode layer at a first surface of the semiconductor device and a second electrode layer at an opposite second surface of the semiconductor device, wherein the first electrode layer of the semiconductor device is attached to the first conduction surface and is electrically connected to the base substrate through the top substrate and the first soldering material, and the second electrode layer of the semiconductor device is superimposed over the second conduction surface and electrically connected to the second routing circuitry through the electrode connection slug and a second soldering material between the second electrode layer of the semiconductor device and the base substrate.
2 . The semiconductor assembly of claim 1 , wherein the first conduction surface has an area of 1 mm 2 or more.
3 . The semiconductor assembly of claim 1 , wherein the second conduction surface has an area of 0.1 mm 2 or more.
4 . The semiconductor assembly of claim 1 , wherein the electrode connection slug has a thickness of 0.1 mm or more.
5 . The semiconductor assembly of claim 1 , wherein the electrode connection plate has a thickness of 0.1 mm or more.
6 . The semiconductor assembly of claim 1 , wherein the base substrate further includes glass fibers impregnated in the dielectric layer.
7 . The semiconductor assembly of claim 1 , wherein the first routing circuitry and the second routing circuitry are electrically connected to each other through vertical connecting elements in the dielectric layer.
8 . The semiconductor assembly of claim 1 , wherein the top substrate has a thermal conductivity greater than 10 W/mK and an electrical resistivity less than 0.1 μohm-m.
9 . The semiconductor assembly of claim 1 , wherein the electrode connection slug has a thermal conductivity greater than 10 W/mK and an electrical resistivity less than 0.1 μohm-m.
10 . The semiconductor assembly of claim 1 , wherein the first conduction surface is attached to the first electrode layer of the semiconductor device using a soldering material having a thermal conductivity greater than 10 W/mK and an electrical resistivity less than 1 μohm-m.
11 . The semiconductor assembly of claim 1 , wherein the first soldering material has a thermal conductivity greater than 10 W/mK and an electrical resistivity less than 1 μohm-m.
12 . The semiconductor assembly of claim 1 , wherein the second soldering material has a thermal conductivity greater than 10 W/mK and an electrical resistivity less than 1 μohm-m.
13 . The semiconductor assembly of claim 1 , wherein no thermal barrier material having a thermal conductivity less than 1 W/mK is present between the first conduction surface of the top substrate and the first electrode layer of the semiconductor device.
14 . The semiconductor assembly of claim 1 , wherein no thermal barrier material having a thermal conductivity less than 1 W/mK is present between the second conduction surface of the base substrate and the second electrode layer of the semiconductor device.
15 . The semiconductor assembly of claim 1 , wherein the flatness control layer includes fibers or fillers in a resin material.
16 . The semiconductor assembly of claim 1 , further comprising an additional device stacked over the flatness control layer and electrically connected to the electrode connection plate.
17 . The semiconductor assembly of claim 16 , wherein the flatness control layer has an opening to accommodate a third soldering material in contact with the additional device and the substantially planar outer surface of the electrode connection plate.