IP Library › Granted Patent US 12,575,452
Granted Patent B2
US 12,575,452 · App. 18/015,371 · Granted Mar 10, 2026

Display module and manufacturing method therefor, and LED display panel and LED display apparatus

Inventors: Zhiqiang Huang (Dongguan, CN); Wuwen Pang (Dongguan, CN); Wenrong Zhuang (Dongguan, CN); Ming Sun (Dongguan, CN); Jingquan Lu (Dongguan, CN)
Assignee: HCP TECHNOLOGY CO., LTD.
H01L25/0753H10H20/84H10H20/853H10H20/034H10H20/0362
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Quick Facts
Patent No.
US 12,575,452
App. No.
18/015,371
Granted
Mar 10, 2026
Kind
B2
Abstract

Provided are a display module and a manufacturing method therefor, an LED display panel and an LED display apparatus. The display module includes a board, a pixel unit array, an encapsulation layer and a black ink layer. The board has a front surface and a back surface. The pixel unit array is disposed on the front surface of the board. The encapsulation layer covers the region where the pixel unit array is located. A side surface of the encapsulation layer forms a slope surface at an edge of the front surface of the board. The black ink layer covers the encapsulation layer.

Claims (36)

1 . A display module, comprising:

a substrate, wherein the substrate has a front surface and a back surface;

a pixel unit array, wherein the pixel unit array is disposed on the front surface of the substrate;

an encapsulation layer, wherein the encapsulation layer covers a region where the pixel unit array is located, and a side surface of the encapsulation layer forms a slope surface at an edge of the front surface of the substrate; and

a black ink layer, wherein the black ink layer covers the encapsulation layer;

wherein one of the following is satisfied:

the slope surface is a chamfer formed by half chamfering the encapsulation layer or fully chamfering the encapsulation layer;

the slope surface comprises at least two sub-slope-surfaces, and the at least two sub-slope-surfaces are arranged in sequence; or

the display module further comprises a memory coating layer, wherein the memory coating layer covers the black ink layer and is configured to protect the black ink layer.

2 . The display module according to claim 1 , wherein in a case where the slope surface is the chamfer formed by half chamfering the encapsulation layer or fully chamfering the encapsulation layer, an angle range of the chamfer is 1 degree to 89 degrees.

3 . The display module according to claim 1 , wherein in a case where the slope surface is the chamfer formed by half chamfering the encapsulation layer or fully chamfering the encapsulation layer or the display module further comprises the memory coating layer, the slope surface comprises a circular arc surface.

4 . The display module according to claim 1 , wherein a vertical projection of the slope surface on the substrate does not overlap the region where the pixel unit array is located.

5 . A manufacturing method for a display module, comprising:

providing a substrate, wherein the substrate has a front surface and a back surface;

forming a pixel unit array on the front surface of the substrate;

forming an encapsulation layer on a region where the pixel unit array is located;

forming a slope surface on a side surface of the encapsulation layer located at an edge of the front surface of the substrate; and

forming a black ink layer on the encapsulation layer;

wherein forming the slope surface on the side surface of the encapsulation layer located at the edge of the front surface of the substrate comprises:

using a milling cutter to cut the side surface of the encapsulation layer located at the edge of the front surface of the substrate to form the slope surface.

6 . The method according to claim 5 , wherein forming the encapsulation layer on the region where the pixel unit array is located comprises:

forming the encapsulation layer by at least one of spraying, spin coating, slot die coating, die pressing, film mounting or dispensing.

7 . A light emitting diode (LED) display module, comprising a plurality of display modules, wherein the plurality of display modules are arranged in an array; and

wherein a display module of the plurality of display modules comprises:

a substrate, wherein the substrate has a front surface and a back surface;

a pixel unit array, wherein the pixel unit array is disposed on the front surface of the substrate;

an encapsulation layer, wherein the encapsulation layer covers a region where the pixel unit array is located, and a side surface of the encapsulation layer forms a slope surface at an edge of the front surface of the substrate; and

a black ink layer, wherein the black ink layer covers the encapsulation layer;

wherein one of the following is satisfied:

the slope surface is a chamfer formed by half chamfering the encapsulation layer or fully chamfering the encapsulation layer;

the slope surface comprises at least two sub-slope-surfaces, and the at least two sub-slope-surfaces are arranged in sequence; or

the display module further comprises a memory coating layer, and the memory coating layer covers the black ink layer and is configured to protect the black ink layer.

8 . A light emitting diode (LED) display screen, comprising a plurality of LED display modules according to claim 7 , wherein the plurality of LED display modules are arranged in an array.

9 . The LED display module according to claim 7 , wherein in a case where the slope surface is the chamfer formed by half chamfering the encapsulation layer or fully chamfering the encapsulation layer, an angle range of the chamfer is 1 degree to 89 degrees.

10 . The LED display module according to claim 7 , wherein in a case where the slope surface is the chamfer formed by half chamfering the encapsulation layer or fully chamfering the encapsulation layer or the display module further comprises the memory coating layer, the slope surface comprises a circular arc surface.

11 . The LED display module according to claim 7 , wherein a vertical projection of the slope surface on the substrate does not overlap the region where the pixel unit array is located.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2023
From: HUANG, ZHIQIANG; PANG, WUWEN; ZHUANG, WENRONG; SUN, MING; LU, JINGQUAN
To: HCP TECHNOLOGY CO., LTD.
Reel/Frame 062328/0692 →
Priority Claims (1)
CN 202010668892.8 · Jul 13, 2020 · national
Continuity (1)
Related Publication 20230282623A1 · Sep 7, 2023
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