Methods and systems for managing memory with dynamic ECC protection
The present disclosure relates to defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.
1 . A method for operating an array of memory cells, comprising:
storing payload in a plurality of memory cells of the array; and
based on a current status of the memory cells, selecting a quantity of parity cells to be used for storing parity data, wherein the quantity of parity cells is within a predefined minimum quantity based on a minimum error correction code (ECC) capability and a predefined maximum quantity based on a maximum ECC capability; and
storing the parity data in the selected quantity of parity cells.
2 . The method of claim 1 , comprising storing a portion of the payload data in at least one of the parity cells not selected to store parity data in response to the quantity of parity cells being less than the predefined maximum.
3 . The method of claim 2 , comprising selecting an increased quantity of parity cells to be used for storing parity data; and
relocating the portion of the payload data stored the at least one parity cell to at least one cell a different codeword in response to the increased quantity of parity cells being selected.
4 . The method of claim 1 , comprising selecting a different quantity of parity cells to be used for storing parity data over the lifetime of the memory cells based on a time-varying status thereof.
5 . The method of claim 1 , comprising selecting a respective quantity of parity cells to be used for storing parity data for each of a plurality of portions of the array based on the status of the memory cells thereof.
6 . The method of claim 5 , comprising storing respective data comprising a respective indication of the respective quantity of parity cells for each of the plurality of portions of the array in a look-up table.
7 . The method of claim 5 , comprising dynamically adapting read and/or write access time to each portion of the array based on a respective quantity of parity cells to be used for storing the payload data in codewords of said portions.
8 . The method of claim 1 , comprising encoding a codeword with additional bits indicative of the selected quantity of parity cells for said codeword.
9 . The method of claim 1 , comprising determining the current status of the memory cells based on a value of a first counter used to count a quantity of accesses to the memory cells or a quantity of refresh events or a quantity of power-up events or a combination thereof.
10 . The method of claim 1 , comprising determining the current status of the memory cells by means of a testing machine.
11 . A memory device comprising:
an array of memory cells; and
a controller coupled to the array, wherein the controller is configured to:
store payload data in a plurality of memory cells of the array;
based on a current status of the memory cells, select a quantity of parity cells to be used for storing parity data, wherein the quantity of parity cells is within a predefined minimum quantity based on a minimum error correction code (ECC) capability and a predefined maximum quantity based on a maximum ECC capability; and
store the parity data in the selected quantity of parity cells.
12 . The memory device of claim 11 , wherein the controller is configured to store a portion of the payload data in at least one of the parity cells not selected to store parity data in response to the quantity of parity cells being less than the predefined maximum.
13 . The memory device of claim 12 , wherein the controller is configured to:
select an increased quantity of parity cells to be used for storing parity data; and
relocate the portion of the payload data stored the at least one parity cell to at least one cell a different codeword in response to the increased quantity of parity cells being selected.
14 . The memory device of claim 11 , wherein the controller is configured to select a different quantity of parity cells to be used for storing parity data over the lifetime of the memory cells based on a time-varying status thereof.
15 . The memory device of claim 11 , wherein the controller is configured to select a respective quantity of parity cells to be used for storing parity data for each of a plurality of portions of the array based on the status of the memory cells thereof.
16 . The memory device of claim 15 , wherein the controller is configured to store respective data comprising a respective indication of the respective quantity of parity cells for each of the plurality of portions of the array in a look-up table.
17 . The memory device of claim 15 , wherein the controller is configured to dynamically adapt read and/or write access time to each portion of the array based on a respective quantity of parity cells to be used for storing the payload data in codewords of said portions.
18 . The memory device of claim 11 , wherein the controller is configured to encode a codeword with additional bits indicative of the selected quantity of parity cells for said codeword.
19 . The memory device of claim 11 , wherein the controller is configured to determine the current status of the memory cells based on a value of a first counter used to count a quantity of accesses to the memory cells or a quantity of refresh events or a quantity of power-up events or a combination thereof.
20 . The memory device of claim 11 , wherein the controller is configured to determine the current status of the memory cells based on input from a testing machine.