Display device
Disclosed is a display device including a display panel including a light emitting element and a pixel circuit connected to the light emitting element, wherein the pixel circuit includes a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second power line, a second transistor connected between the second electrode of the first transistor and a data line to receive a write scan signal, a third transistor connected between the first node and the first electrode of the first transistor to receive a compensation scan signal, a storage capacitor connected between the first node and the second power line, and a fourth transistor connected between the storage capacitor and the second power line to receive a first emission control signal.
1 . A display device comprising:
a display panel including a light emitting element and a pixel circuit connected to the light emitting element,
wherein the pixel circuit includes:
a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second power line;
a second transistor connected between the second electrode of the first transistor and a data line to receive a write scan signal;
a third transistor connected between the first node and the first electrode of the first transistor to receive a compensation scan signal which is different from the write scan signal;
a storage capacitor connected between the first node and the second power line; and
a fourth transistor connected between the storage capacitor and the second power line to receive a first emission control signal,
wherein the display panel displays an image in a plurality of frames,
wherein the plurality of frames includes a write frame and a holding frame,
wherein the write scan signal and the compensation scan signal have an active level in the write frame, and
wherein the write scan signal has the active level in the holding frame, and the compensation scan signal only has an inactive level during the holding frame.
2 . The display device of claim 1 , wherein at least one of the plurality of frames includes a first initialization interval, a compensation interval following the first initialization interval, a second initialization interval following the compensation interval, and an emission interval following the second initialization interval,
wherein the compensation scan signal has an active level and the write scan signal and the first emission control signal has an inactive level during the first initialization interval, and
wherein the compensation scan signal has the active level and the first emission control signal has the inactive level during the compensation interval;
wherein the first emission control signal has an active level, and the write scan signal and the compensation scan signal have the inactive level during the second initialization interval,
wherein the compensation interval includes a data write interval in which the write scan signal has an active level.
3 . The display device of claim 1 , wherein the pixel circuit further includes a fifth transistor connected between a second node connected to the storage capacitor and the fourth transistor, and a reference voltage line.
4 . The display device of claim 3 , wherein at least one of the plurality of frames includes a first initialization interval, a compensation interval following the first initialization interval, a second initialization interval following the compensation interval, and an emission interval following the second initialization interval,
wherein the fifth transistor receives one of the compensation scan signal and a black scan signal,
wherein the one of the compensation scan signal and the black scan signal received by the fifth transistor has an active level during the first initialization interval and the compensation interval, and has an inactive level during the second initialization interval.
5 . The display device of claim 1 , wherein the pixel circuit further includes a sixth transistor connected between the second electrode of the first transistor and the second power line to receive the first emission control signal.
6 . The display device of claim 5 , wherein the pixel circuit further includes a seventh transistor connected between the first power line and the first electrode of the first transistor to receive a second emission control signal.
7 . The display device of claim 6 ,
wherein the second emission control signal corresponds to an i-th light emission control signal that are sequentially activated, where “i” is a natural number, and
wherein the first emission control signal corresponds to an (i−k)-th emission control signal that are sequentially activated, where “k” is a natural number less than or equal to “i”.
8 . The display device of claim 7 , wherein at least one of the plurality of frames includes a first initialization interval, a compensation interval following the first initialization interval, a second initialization interval following the compensation interval, and an emission interval following the second initialization interval,
wherein the first emission control signal has an active level, and the second emission control signal has an inactive level during the second initialization interval, and
wherein the first emission control signal and the second emission control signal have the active level during the emission interval.
9 . The display device of claim 5 , wherein the light emitting element includes:
an anode connected to a third node which is connected to the fourth transistor and the sixth transistor; and
a cathode connected to the second power line.
10 . The display device of claim 9 , wherein the pixel circuit further includes an eighth transistor connected between the third node and an initialization voltage line to receive a black scan signal.
11 . The display device of claim 10 , wherein at least one of the plurality of frames includes a first initialization interval, a compensation interval following the first initialization interval, a second initialization interval following the compensation interval, and an emission interval following the second initialization interval,
wherein the black scan signal has an active level during the first initialization interval and the compensation interval, and has an inactive level during the second initialization interval.
12 . The display device of claim 11 , wherein the compensation scan signal has an active level during the compensation interval and an inactive level during the second initialization interval, and
wherein the black scan signal is inactivated after the compensation scan signal is inactivated.
13 . The display device of claim 11 ,
wherein the black scan signal has the active level in the write frame and the holding frame.
14 . The display device of claim 10 , wherein the pixel circuit further includes a fifth transistor connected between a second node connected to the storage capacitor and the fourth transistor, and a reference voltage line to receive the black scan signal.
15 . The display device of claim 10 , wherein the first transistor further includes a back-gate electrode connected to the third node which is connected to the anode of the light emitting element.
16 . The display device of claim 5 , wherein the light emitting element includes:
an anode connected to the first power line; and
a cathode connected to the first electrode of the first transistor.
17 . The display device of claim 16 , wherein the pixel circuit further includes an eighth transistor connected between the cathode of the light emitting element and an initialization voltage line to receive a black scan signal.
18 . The display device of claim 16 , wherein the first transistor further includes a back-gate electrode connected to the second power line.
19 . The display device of claim 1 , wherein the first transistor further includes a back-gate electrode connected to a gate initialization voltage line.