Voltage regulator with programmable telemetry configuration

1 . An apparatus comprising:

a processor;

a voltage regulator configured to supply power to the processor; and

a voltage regulator controller comprising:

a current sensor comprising an analog-to-digital converter (ADC) having an ADC input range and configured to provide current data based on an ADC input voltage; and

a configuration manager configured to receive processor power data and adjust a scale and/or an offset of the ADC input range based on the processor power data.

2 . The apparatus of claim 1 , wherein:

the ADC has an ADC input range offset:

the configuration manager is configured to adjust the offset of the ADC input range by adjusting the ADC input range offset.

3 . The apparatus of claim 1 , wherein the voltage regulator controller further comprises:

a telemetry manager configured to receive power data from the ADC and to transmit the power data to the processor.

4 . The apparatus of claim 3 , wherein the configuration manager is configured to adjust a telemetry offset based on the power data.

5 . The apparatus of claim 1 , further comprising a reference resistor, wherein:

the ADC input voltage is based on an electric potential across the reference resistor.

6 . The apparatus of claim 1 , wherein the configuration manager is configured to receive the processor power data from the processor.

7 . The apparatus of claim 1 , wherein:

the processor has a low power mode and a high power mode;

the ADC input range has a lower value when the processor operates in the low power mode; and

the ADC input range has a higher value when the processor operates in the high power mode.

8 . The apparatus of claim 1 , wherein:

the processor has a plurality of operational states including a low power mode and a high power mode; and

the processor power data includes a low power indication when the processor operates in the low power mode.

9 . The apparatus of claim 8 , wherein:

a least significant bit of the ADC represents a first voltage when the processor operates in the low power mode;

the least significant bit of the ADC represents a second voltage when the processor operates in the high power mode; and

the second voltage is greater than the first voltage.

10 . The apparatus of claim 9 , wherein the second voltage is at least 50% greater than the first voltage.

11 . The apparatus of claim 8 , wherein the voltage regulator controller improves a power efficiency of the apparatus when the processor is in the low power mode.

12 . The apparatus of claim 1 , wherein the processor is a central processor unit (CPU), a graphics processor unit (GPU), or an accelerated processor unit (APU).

13 . The apparatus of claim 1 , wherein the apparatus is a computer device.

14 . The apparatus of claim 1 , wherein:

the processor has a multiphase power supply:

the voltage regulator comprises a plurality of phase current sensors;

each phase current sensor of the plurality of phase current sensors comprises a respective ADC providing a phase current to a current summer; and

the current summer provides a summed current value.

15 . A computer-implemented method for controlling a voltage regulator, at least a portion of the computer-implemented method being performed by a device comprising at least one processor, the computer-implemented method comprising:

setting a scale parameter for an analog-to-digital converter (ADC) to an initial scale parameter;

measuring a processor current for a processor using the ADC;

transmitting a processor power to the processor;

receiving a processor power signal indicating a change in the processor power; and

adjusting the scale parameter to a second scale parameter based on the change in the processor power.

16 . The computer-implemented method of claim 15 , further comprising:

measuring a second processor current using the ADC and the second scale parameter; and

transmitting a second processor power to the processor.

17 . The computer-implemented method of claim 15 , wherein:

the initial scale parameter is an initial current per least significant bit of the ADC; and

the second scale parameter is a second current per least significant bit of the ADC.

18 . The computer-implemented method of claim 15 , wherein:

the processor power signal indicating the change in the processor power indicates a low power operation of the processor.

19 . A non-transitory computer-readable medium comprising one or more computer-executable instructions that, when executed by a computing device, cause the computing device to:

receive a signal indicating low power operation of a processor;

adjust a scale parameter of an analog-to-digital converter (ADC) to a low power scale parameter;

measure processor current data using the ADC based on the low power scale parameter; and

transmit processor power data to the processor.

20 . The non-transitory computer-readable medium of claim 19 , wherein the one or more computer-executable instructions that, when executed by the computing device, further cause the computing device to:

receive a signal indicating a change in an operational power of the processor; and

adjust the scale parameter of the analog-to-digital converter based on the change in the operational power of the processor.