IP Library › Granted Patent US 12,580,674
Granted Patent B2
US 12,580,674 · App. 18/392,452 · Granted Mar 17, 2026

Flexible forwarded clocking architecture for dense wavelength division multiplexing systems

Inventors: Sanquan Song (Los Altos Hills, CA); Nikola Nedovic (San Jose, CA); Thomas Hastings Greer, III (Chapel Hill, NC); Carl Thomas Gray (Apex, NC)
Assignee: NVIDIA Corp.
H04J14/02862H04B10/613H04J14/0267
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Quick Facts
Patent No.
US 12,580,674
App. No.
18/392,452
Granted
Mar 17, 2026
Kind
B2
Abstract

A dense wave division multiplex (DWDM) receiver includes receiver lanes each configured to detect signals encoded in a different electromagnetic frequency band. The DWDM receiver applies a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network, and receiver lanes that are configured to receive data signals generate resonance on the clock distribution network. The resonant signal from the clock distribution network is applied to sample the received data signals.

Claims (31)

1 . A dense wave division multiplex (DWDM) receiver comprising:

a plurality of receiver lanes;

logic to apply a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network; and

wherein one or more of the receiver lanes are configured to receive data signals and to generate resonance on the clock distribution network.

2 . The DWDM receiver of claim 1 , further comprising logic to selectively enable and disable the resonance generated by the receiver lanes configured to receive the data signals.

3 . The DWDM receiver of claim 1 , further comprising logic to selectively exclude the data signals from the receiver lanes configured to receive the data signals from being applied to the clock distribution network.

4 . The DWDM receiver of claim 1 , further configured to apply resonant signals from the clock distribution network to data samplers of the receiver lanes configured to receive the data signals.

5 . The DWDM receiver of claim 1 , the receiver lanes further comprising differential outputs to the clock distribution network.

6 . The DWDM receiver of claim 1 , the receiver lanes further comprising In-phase (I) and Quadrature-phase (Q) outputs to the clock distribution network.

7 . The DWDM receiver of claim 1 , the receiver lanes configured to enable a 1:9 injection ratio for the ILO.

8 . The DWDM receiver of claim 1 , the receiver lanes configured to enable a 1:4 injection ratio for the ILO.

9 . A transceiver comprising:

a transmitter comprising a plurality of transmitter lanes;

a receiver comprising:

a plurality of receiver lanes;

logic to apply a clock signal forwarded from a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network; and

logic to selectively enable one or more of the receiver lanes to generate resonance on the clock distribution network.

10 . The transceiver of claim 9 , wherein the transmitter is a dense wave division multiplex (DWDM) transmitter and the receiver is a DWDM receiver.

11 . The transceiver of claim 9 , further comprising logic to selectively configure one or more of the receiver lanes to exclude received signals from reaching the clock distribution network.

12 . The transceiver of claim 9 , wherein the clock distribution network is coupled to clock data sampling circuits of one or more of the receiver lanes.

13 . The transceiver of claim 9 , wherein one or more of the receiver lanes comprises a differential output to the clock distribution network.

14 . The transceiver of claim 9 , wherein one or more of the receiver lanes comprises an In-phase (I) and Quadrature-phase (Q) output to the clock distribution network.

15 . The transceiver of claim 9 , further comprising logic to configure an injection ratio of the ILO.

16 . The transceiver of claim 15 , wherein the ILO is configured with a 1:9 injection ratio.

17 . The transceiver of claim 15 , wherein the ILO is configured with a 1:4 injection ratio.

18 . An optical receiver comprising:

a plurality of receiver lanes;

logic to apply a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network; and

logic to set an injection ratio of the ILO by selectively enabling and disabling individual ones of the receiver lanes to generate resonance on the clock distribution network.

19 . The optical receiver of claim 18 , wherein one or more of the receiver lanes comprises a differential output to the clock distribution network.

20 . The optical receiver of claim 18 , wherein one or more of the receiver lanes comprises an In-phase (I) and Quadrature-phase (Q) output to the clock distribution network.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2024
From: SONG, SANQUAN; NEDOVIC, NIKOLA; GREER III, THOMAS HASTINGS; GRAY, CARL THOMAS
To: NVIDIA CORP.
Reel/Frame 066330/0407 →
Continuity (1)
Related Publication 20250211359A1 · Jun 26, 2025
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