Granted Patent B2

US 12,580,790 · App. 18/155,094 · Granted Mar 17, 2026

Inventors: Avneep Kumar Goyal (Greater Noida, IN); Nicolas Guion (Change, FR); Sumit Kumar Singhal (Jaipur, IN); Jagtar Singh (Faridabad, IN); Dhulipalla Phaneendra Kumar (Bangalore, IN)

Assignee: STMICROELECTRONICS INTERNATIONAL N.V.

H04L12/40143H04L2012/40215

Abstract

Claims (55)

1 . An apparatus implementing a message-based protocol interface with a communication bus, the apparatus comprising:

message handler core circuitry comprising:

a transmit message buffer,

wherein the transmit message buffer is configured to store at least a first portion of a transmit message;

a transmit FIFO, wherein the transmit FIFO is configured to store at least a second portion of the transmit message, and

receive handler circuitry configured to store at least a portion of a received message;

a transmit data memory configured to store a plurality of transmit messages including at least the transmit message; and

a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to:

select the transmit message from the plurality of transmit messages based on a transmit message priority;

transmit at least the first portion of the transmit message from the transmit data memory to the transmit message buffer associated with the message handler core circuitry;

transmit at least the second portion of the transmit message from the transmit data memory to the transmit FIFO associated with the message handler core circuitry; and

receive the received message from the receive handler circuitry into a receive data memory.

2 . The apparatus of claim 1 , wherein the message-based protocol is a controller area network extra-long (CAN-XL) protocol.

3 . The apparatus of claim 2 , wherein the apparatus further supports operation in accordance with a Classic CAN protocol and a CAN FD protocol.

4 . The apparatus of claim 1 , further comprising:

protocol control circuitry configured to:

generate an output sequence encoding an outgoing message based at least in part on the transmit message and in accordance with the message-based protocol, and

receive an input sequence encoding the received message in accordance with the message-based protocol.

5 . The apparatus of claim 4 , wherein the transmit message buffer is configured to store at least a portion of the plurality of transmit messages, and a selected transmit message is selected from the plurality of transmit messages based on the portions of the plurality of transmit messages in the transmit message buffer.

6 . The apparatus of claim 5 , wherein the message handler core circuitry further comprises:

a priority decoder,

wherein the priority decoder is configured to select the selected transmit message based at least in part on a transmit message priority indicated in the portion of the transmit message stored in the transmit message buffer.

7 . The apparatus of claim 6 , wherein in an instance in which the priority decoder determines a high priority message stored in the transmit message buffer has a higher transmit message priority than the transmit message priority of the selected transmit message, the portion of the selected transmit message stored in the transmit FIFO is replaced with a portion of the high priority message.

8 . The apparatus of claim 1 , wherein the transmit message is selected from the transmit data memory based on a transmit message priority included in the first portion of the transmit message and-wherein, in an instance in which the transmit message is selected by the message handler core circuitry to be transmitted, the second portion of the transmit message is transmitted to the transmit FIFO.

9 . The apparatus of claim 1 , wherein a payload size of the transmit message is bigger than a maximum capacity of the transmit FIFO, and wherein the transmit message is transmitted to the transmit FIFO in portions according to a paging scheme.

10 . The apparatus of claim 1 , further comprising a buffer status generator, wherein the buffer status generator is configured to generate a buffer status code indicating a status of the transmit message buffer.

11 . The apparatus of claim 10 , wherein the message handler processor updates the transmit FIFO based on the buffer status code after updating a software-programmable message buffer request bit.

12 . The apparatus of claim 1 , wherein the transmit message buffer is configured to store the portion of two transmit messages, and wherein the transmit FIFO is configured to store the second portion of one selected transmit message.

13 . The apparatus of claim 1 , wherein the transmit data memory is configured to store a plurality of transmit messages.

14 . The apparatus of claim 1 , wherein the receive data memory is configured to store a plurality of received messages.

15 . A computer-implemented method for transmitting messages on a communication bus in compliance with a message-based protocol, the computer-implemented method comprising:

receiving, at a message handler processor, a plurality of transmit messages,

wherein the message handler processor comprises a processor and an instruction memory including program code;

storing the plurality of transmit messages in a transmit data memory;

selecting, a transmit message from the plurality of transmit messages based on a transmit message priority associated with the transmit message;

transmitting at least a first portion of the transmit message from the transmit data memory to a transmit message buffer associated with message handler core circuitry;

receiving, from the message handler core circuitry, notification of a selected transmit message; and

transmitting at least a second portion of the transmit message, comprising at least a payload, from the transmit data memory to a transmit FIFO associated with the message handler core circuitry to be transmitted on the communication bus.

16 . The computer-implemented method of claim 15 , wherein the message-based protocol is a controller area network extra-long (CAN-XL) protocol.

17 . The computer-implemented method of claim 15 , wherein the message handler processor comprises a combination of software and hardware components and the message handler core circuitry comprises hardware components.

18 . The computer-implemented method of claim 17 , further comprising:

receiving, from the message handler core circuitry a received message; and

storing the received message in a receive data memory.

19 . An apparatus implementing a message-based protocol interface with a communication bus, the apparatus comprising:

message handler core circuitry comprising:

a transmit message buffer,

wherein the transmit message buffer is configured to store a first portion of a selected transmit message;

a transmit FIFO,

wherein at least a second portion of the selected transmit message is transmitted by a message handler processor to the transmit FIFO,

wherein a payload size of the selected transmit message is bigger than a maximum capacity of the transmit FIFO, and

wherein the transmit message is transmitted to the transmit FIFO in portions according to a paging scheme;

receive handler circuitry configured to store at least a portion of a received message; and

the message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to:

transmit the second portion of the selected transmit message to the transmit FIFO; and

receive the received message from the receive handler circuitry into a receive data memory.

Assignments (3)

Continuity (1)

References Cited (13)