IP Library › Granted Patent US 12,581,220
Granted Patent B2
US 12,581,220 · App. 18/001,299 · Granted Mar 17, 2026

Imaging device having insulated amplification transistor

Inventors: Kyosuke Yamada (Kanagawa, JP); Atsuhiko Yamamoto (Kanagawa, JP); Takashi Machida (Tokyo, JP); Hideo Kido (Kanagawa, JP); Ryo Fukui (Kanagawa, JP); Yu Shiihara (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N25/78H10F39/802H10F39/8037H10F39/811
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Quick Facts
Patent No.
US 12,581,220
App. No.
18/001,299
Granted
Mar 17, 2026
Kind
B2
Abstract

Provided is an imaging device capable of suppressing deterioration in characteristics. The imaging device includes a first substrate portion and a second substrate portion on one surface side of the first substrate portion. The first substrate portion includes a sensor pixel, a first interlayer insulating film, and a first electrode portion. The second substrate portion includes a readout circuit, a second interlayer insulating film, and a second electrode portion. The first electrode portion and the second electrode portion are directly joined to each other. The second semiconductor substrate includes a first element region in which an amplification transistor is provided, a second element region in which another element is provided, and a through region through which the second semiconductor substrate passes in the thickness direction. The first element region and the second element region are isolated by the through region.

Claims (98)

1 . An imaging device, comprising:

a plurality of pixels,

wherein each pixel of the plurality of pixels comprises:

a pixel region including a sensor pixel including a photoelectric conversion element;

a peripheral region positioned at a periphery of the pixel region such as to exclude the sensor pixel from being provided within the peripheral region,

a first substrate portion; and

a second substrate portion provided on one surface side of the first substrate portion,

wherein the first substrate portion comprises:

a first semiconductor substrate;

the sensor pixel provided at the first semiconductor substrate, the sensor pixel configured to perform photoelectric conversion;

a first interlayer insulating film provided at the first semiconductor substrate on a side of a surface facing the second substrate portion; and

a first electrode portion provided at the first interlayer insulating film on a side of a surface facing the second substrate portion,

wherein the second substrate portion comprises:

a second semiconductor substrate;

a readout circuit provided at the second semiconductor substrate,

wherein the readout circuit configured to output a pixel signal based on a charge output from the sensor pixel;

a second interlayer insulating film provided at the second semiconductor substrate on a side of a surface facing the first substrate portion; and

a second electrode portion provided at the second interlayer insulating film on a side of a surface facing the first substrate portion,

wherein the first electrode portion and the second electrode portion are directly joined to each other,

wherein the readout circuit comprises:

an amplification transistor configured to amplify a signal of a voltage corresponding to a level of the charge output from the sensor pixel,

wherein the second semiconductor substrate includes:

a first element region in which the amplification transistor is provided;

a second element region in which another element other than the amplification transistor is provided; and

a through region through which the second semiconductor substrate passes in a thickness direction,

wherein the first element region and the second element region are isolated by the through region, and

wherein the amplification transistor is provided within the pixel region and the another element other than the amplification transistor is provided within the peripheral region in a cross-sectional view.

2 . The imaging device according to claim 1 , wherein a source region of the amplification transistor and a well region of the amplification transistor are connected.

3 . The imaging device according to claim 1 , further comprising:

a third substrate portion provided at the second substrate portion on an opposite side of a surface facing the first substrate portion,

wherein the second substrate portion further comprises:

a third interlayer insulating film provided at the second semiconductor substrate on a side of a surface facing the third substrate portion; and

a third electrode portion provided at the third interlayer insulating film on a side of a surface facing the third substrate portion,

wherein the third substrate portion comprises:

a third semiconductor substrate;

a logic circuit provided at the third semiconductor substrate, the logic circuit configured to process the pixel signal;

a fourth interlayer insulating film provided at the third semiconductor substrate on a side of a surface facing the second substrate portion; and

a fourth electrode portion provided at the fourth interlayer insulating film on a side of a surface facing the second substrate portion, and

wherein the third electrode portion and the fourth electrode portion are directly joined to each other.

4 . The imaging device according to claim 1 , wherein the sensor pixel further comprises:

a photoelectric conversion element;

a transfer transistor electrically connected to the photoelectric conversion element; and

a floating diffusion configured to temporarily hold a charge output from the photoelectric conversion element via the transfer transistor,

wherein the readout circuit further comprises:

a reset transistor configured to reset a potential of the floating diffusion to a predetermined potential; and

a selection transistor configured to control an output timing of the pixel signal from the amplification transistor,

wherein the amplification transistor generates, as the pixel signal, a signal of a voltage corresponding to a level of a charge held in the floating diffusion, and

wherein the another element provided in the second element region includes the reset transistor.

5 . The imaging device according to claim 4 , wherein the first substrate portion further comprises a first wiring line connected to the floating diffusion,

wherein the second substrate portion further comprises a second wiring line connected to a gate electrode of the amplification transistor, and

wherein the first wiring line and the second wiring line are connected to each other via the first electrode portion and the second electrode portion.

6 . The imaging device according to claim 1 , wherein the second substrate portion further comprises:

an insulating isolation film provided in the through region; and

a through wiring line passing through the insulating isolation film.

7 . The imaging device according to claim 5 , wherein the second substrate portion further comprises:

an insulating isolation film provided in the through region; and

a through wiring line passing through the insulating isolation film, and

wherein a part of the second wiring line passes through the insulating isolation film as the through wiring line.

8 . The imaging device according to claim 6 , wherein the second substrate portion further comprises a first air gap portion provided at the insulating isolation film and positioned between the through wiring line and a side surface of the first element region.

9 . The imaging device according to claim 8 , wherein the first air gap portion is positioned between the through wiring line and a well region of the amplification transistor.

10 . The imaging device according to claim 6 , wherein

the second substrate portion further comprises a second air gap portion provided at the insulating isolation film and positioned between the through wiring line and a side surface of the second element region.

11 . The imaging device according to claim 4 , wherein the another element provided in the second element region includes the reset transistor, and

wherein the second substrate portion further comprises:

an insulating isolation film provided in the through region;

a through wiring line passing through the insulating isolation film; and

a second air gap portion provided at the insulating isolation film and positioned between the through wiring line and a well region of the reset transistor.

12 . The imaging device according to claim 5 , wherein the first wiring line and the second wiring line are arranged in the pixel region.

13 . The imaging device according to claim 1 , wherein the sensor pixel further comprises a MEM unit.

14 . The imaging device according to claim 1 , further comprising a third substrate portion provided at the second substrate portion on an opposite side of a surface facing the first substrate portion.

15 . The imaging device according to claim 14 , wherein the third substrate portion comprises a third semiconductor substrate and a logic circuit provided at the third semiconductor substrate.

16 . An imaging device, comprising:

a plurality of pixels,

wherein each pixel of the plurality of pixels comprises:

a pixel region including a sensor pixel including a photoelectric conversion element;

a peripheral region positioned at a periphery of the pixel region such as to exclude the sensor pixel from being provided within the peripheral region;

a first substrate portion; and

a second substrate portion provided on one surface side of the first substrate portion,

wherein the first substrate portion comprises:

a first semiconductor substrate; and

the sensor pixel provided at the first semiconductor substrate;

wherein the second substrate portion comprises:

a second semiconductor substrate; and

a readout circuit provided at the second semiconductor substrate,

wherein the readout circuit comprises an amplification transistor,

wherein the second semiconductor substrate includes:

a first element region in which the amplification transistor is provided; and

a second element region in which another element other than the amplification transistor is provided; and

wherein the first element region and the second element region are isolated by a through region, and

wherein the amplification transistor is provided within the pixel region and the another element other than the amplification transistor is provided within the peripheral region in a cross-sectional view.

17 . The imaging device according to claim 16 , wherein a source region of the amplification transistor and a well region of the amplification transistor are connected.

18 . The imaging device according to claim 16 , wherein the sensor pixel further comprises a MEM unit.

19 . The imaging device according to claim 16 , wherein the sensor pixel further comprises:

a photoelectric conversion element;

a transfer transistor electrically connected to the photoelectric conversion element; and

a floating diffusion configured to temporarily hold a charge output from the photoelectric conversion element via the transfer transistor.

20 . The imaging device according to claim 19 , wherein the first substrate portion further comprises a first wiring line connected to the floating diffusion, and

wherein the second substrate portion further comprises a second wiring line connected to a gate electrode of the amplification transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2022
From: YAMADA, KYOSUKE; YAMAMOTO, ATSUHIKO; MACHIDA, TAKASHI; KIDO, HIDEO; FUKUI, RYO; SHIIHARA, YU
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 062086/0688 →
Priority Claims (1)
JP 2020-103558 · Jun 16, 2020 · national
Continuity (1)
Related Publication 20230254608A1 · Aug 10, 2023
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